Choon Beng Sia

A Scalable RFCMOS Noise Model

This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time.

Accurate and scalable RF interconnect model for silicon-based RFIC applications

A new figure of merit, intrinsic factor for interconnects, is proposed to provide insights as to how back-end metallization influences the performance of radio frequency integrated circuits. An accurate and scalable double-/spl pi/ radio frequency interconnect model, continuous across physical dimensions of width and length, is presented to demonstrate reliable predictions of interconnect characteristics up to 10 GHz. Using this interconnect model in gigahertz amplifier and voltage-controlled oscillator circuit simulations yields excellent correlations between simulated and on-wafer measured circuit results.

RFCMOS Unit Width Optimization Technique

In this paper, we demonstrate a unit width ( Wf) optimization technique based on their unity short-circuit current gain frequency (fT) unilateral power gain frequency (fMAX)? and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the Wf change is different; hence, some tradeoff is required to obtain the optimum Wf value. During the HF noise analysis, a new FOM is proposed to study the Wf effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in Wf does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistors layout and helps to select the optimum Wf for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuits performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum Wf for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.

Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.

Modeling and Layout Optimization Techniques for Silicon-Based Symmetrical Spiral Inductors

A scalable and highly accurate RF symmetrical inductor model (with model error of less than 5%) has been developed from more than 100 test structures, enabling device performance versus layout size trade-ofis and optimization up to 10GHz. Large conductor width designs are found to yield good performance for inductors with small inductance values. However, as inductance or frequency increases, interactions between metallization resistive and substrate losses render the use of large widths unfavorable as they consume silicon area and degrade device performance. These flndings are particularly important when exploiting the cost-efiective silicon-based RF technologies for applications with operating frequencies greater than 2.5GHz.

Novel RF process monitoring test structure for silicon devices

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.

True Kelvin CMOS Test Structure to achieve accurate and repeatable DC wafer-level measurements for device modelling applications

A 6-pad True Kelvin Test Structure for advanced CMOS devices is proposed in this work. It allows test engineers to make very accurate and repeatable wafer-level measurements required for SPICE modelling applications. This design helps to overcome parasitic resistance of the probe holder and probe which is found to be dependent on test temperatures. It also mitigates increase in probe contact resistance due to oxidation of exposed underlying copper on aluminum capped test pads as a result of repeated probing at elevated temperatures. Most important of all, it enables accurate device measurements with minimal probe scrub, essential for 30 micrometers or less test pads, without the need for frequent probe tip cleaning.

Minimizing discontinuities in wafer-level sub-THz measurements up to 750 GHz for device modelling applications

Achieving accurate and continuous measurement for sub-THz wafer-level device characterization is particularly important for device modelling applications. This paper outlines, for the first time, challenges affecting measurement continuity and accuracy at such high frequencies. The newly proposed sub-THz measurement strategy with pre-calibration check for low probe contact resistance, combining power and S-parameter probe tip calibration, implementing post-calibration verification checks and ensuring consistent and accurate DC biasing of devices across all frequency bands, has been demonstrated in this work to improve measurement continuity and quality of wafer-level measurements up to 750 GHz.

Scalable RFCMOS Model for 90 nm Technology

This paper presents the formation of the parasitic components that exist in the RF MOSFET structure during its high-frequency operation. The parasitic components are extracted from the transistors S-parameter measurement, and its geometry dependence is studied with respect to its layout structure. Physical geometry equations are proposed to represent these parasitic components, and by implementing them into the RF model, a scalable RFCMOS model, that is, valid up to 49.85 GHz is demonstrated. A new verification technique is proposed to verify the quality of the developed scalable RFCMOS model. The proposed technique can shorten the verification time of the scalable RFCMOS model and ensure that the coded scalable model file is error-free and thus more reliable to use.

Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling

Various structures of on-wafer interconnect for CMOS RFICs fabricated by using 0.18um CMOS are investigated experimentally. The measured S-parameters in terms of the dimensions and frequencies are presented in the paper. Frequency dependence elements of interconnect is extracted from the measurement. A scalable physical model is derived and quantified using measurement results for straight top-metal interconnect.