Christopher N. Collins

High performance Flash memory for 65 nm embedded automotive application

In this paper the results obtained for a new process flow that integrates a high performance flash cell for automotive application with a state of the art 65nm CMOS have been presented. Despite the several specific process steps introduced for the first time on embedded technologies, the MOS performances have not been impacted by the integration of the Flash cell and the related HV MOS and the results obtained on a 4Mbit Flash array are very promising.

Electrical design and performance of a multichip module on a silicon interposer

A multichip module package has been designed in IBMs silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections <; 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.

Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

We integrated a copper TSV (Through Silicon Via) cell in a qualified 32SOI CMOS logic technology with high-K/metal gate and DT (Deep Trench) capacitors. Extensive wafer level characterization and reliability stressing were performed to evaluate the impact of the TSVs and 3D (3-Dimensional) integration processing on device and back end of line reliability performance. This included bias temperature instability stress, hot carrier injection, thermal cycling, wiring electromigration testing, and time-dependent dielectric breakdown studies. The integration of the TSV and process shows an equivalent reliability performance with respect to the 2D baseline for FEOL (Front End of Line) and BEOL (Back End of Line) structures within the assigned 3D design rules. In particular it is demonstrated that this TSV design allows BEOL structures at zero proximity to the KOZ (Keep Out Zone). Further, device and functional data indicate that there is no change in end of life reliability targets from TSV processing and/or proximity.

Synthesis and Control of Ultra Thin Gate Oxides for the 90 and 65 NM Nodes

Thin gate oxide processes for advanced semiconductor manufacturing present many challenges at both the 90 and 65 nm technology nodes. In most cases the films are oxynitride materials (SiO/sub x/N/sub y/) constructed in single wafer tools clustered on the same common platform. The combination of discrete process chambers and the atomic dimensions of the dielectric puts a premium on film characterization and process control. The electrical specifications are severe with common values of /spl plusmn/1 /spl Aring/ leading to nitrogen and oxygen dose requirements of better than /spl plusmn/5E14 at/cm/sup 2/. In the recent past difficulties maintaining those specifications have repeatedly lead to tool down situations and limited run paths. In the aftermath of those events, the investigations which followed exposed weaknesses in both the metrology and the qualification strategies used to characterize those processes. In this paper, a number of examples will be presented which illustrate the sensitivity of the composite process to excursions in any of its component steps. The relative sensitivities of different in-line measurement techniques (optical, electrical, and chemical) will be reported and the data used to illustrate the clear advantages of in-line compositional analysis.