Jaime D. Morillo

New paradigm in lens metrology for lithographic scanner: evaluation and exploration

A new paradigm of lens metrology, which is an on-board in-situ interferometer on a scanner, is evaluated. We called this system as Inline PMI and is based on a shearing type interferometer. Wavefront gradient data is measured and used to reconstruct a full high resolution wavefront. The system was evaluated based on short term and long term stabilities, sensitivity towards system parameters, correlation studies with PMI, a resist-based lens metrology tool and lithographic tests to establish accuracy, and model compliance test against lens model prediction. The lens was detuned with Z7-tilt and Z9 offset to extend the dynamic range of the tests. The metrology demonstrated good repeatability, accuracy and stability as well insensitivity toward environmental parameters and good compliance with lens model predictions. In addition, because of the high resolution nature of the inline PMI system high spatial frequency wavefront content can be recovered. With a derived transfer function we can recover approximately up a spatial frequency of 30 to 40 cycles/pupil diameter. This fills the gap in the power spectrum obtained by low order Zernike terms and traditional high frequency flare measurement from techniques such as disappearing pads. Inline PMI may thus enables a more complete analysis of flare in lithography, which is critical to evaluating double exposure techniques as well as bright field masks with widely varying pattern density. Overall, this on-board interferometry shows good technical performance and fast turnaround time, both of which are essential requirement in low k1-imaging in a manufacturing environment.

Simultaneous critical dimension and overlay measurements on a SEM through target design for inline manufacturing lithography control

This paper introduces the capability of measuring overlay (OL) errors (current level to prior level errors and neighboring field errors) and critical dimension (CD) errors simultaneously on a Critical Dimension Scanning Electron Microscope (CD SEM). In the past OL errors and CD errors have been measured on different tools sets. CD errors have always been measured on SEMs and OL errors have always been measured on optical tools. In both cases, measurements were obtained on separate target designs. The key to this paper is in the design of the targets. We combine, in one target design, the ability to extract OL and CD errors simultaneously. Current OL targets designs are limited by the resolution of that type of tool which is on the order of 1um, this means that current OL target designs are created at ground rules larger than this (typically 2-3um in size) and at ground rules much larger than the circuit design. A target design that allows the OL and CD to be measured at the ground rules of the circuit would be a much more desirable measurement and takes advantage of the SEMs strengths which include resolution. Additionally, a target design that allows current level to prior level OL, neighboring field OL and CD errors to be measured simultaneously would be extremely desirable. The key is designing the targets for cases where prior level information can be seen on the SEM, this can be performed on many levels throughout chip construction, probably more than half of all levels. This methodology will significantly reduce the time it takes to build parts, improve technical performance and save tool cost.

Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

Abstract. We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.

Computational enablement for designs with sub-20nm metal tip to tip using cut shapes from grapho-epitaxy directed self-assembly

This paper presents a design and technology co-optimization (DTCO) study of metal cut formation in the sub-20-nmregime. We propose to form the cuts by applying grapho-epitaxial directed self-assembly. The construction of a DTCO flow is explained and results of a process variation analysis are presented. We examined two different DSA models and evaluated their performance and speed tradeoff. The applicability of each model type in DTCO is discussed and categorized.