Chun-Yung Sung

Amorphization/templated recrystallization method for changing the orientation of single-crystal silicon: An alternative approach to hybrid orientation substrates

We demonstrate that the crystal orientation of single-crystal silicon layers may be changed in selected areas from one orientation to another by an amorphization/templated recrystallization (ATR) process, and then introduce ATR as an alternative approach for fabricating planar hybrid orientation substrates with surface regions of (100)- and (110)-oriented Si. The ATR technique, applied to a starting substrate comprising a thin (50–200 nm) overlayer of (100) or (110) Si on a (110) or (100) Si handle wafer, consists of two process steps: (i) Si+ or Ge+ ion implantation to create an amorphous silicon (a-Si) layer extending from the top of the overlayer to a depth below the overlayer/handle wafer interface, and (ii) a thermal anneal to produce the handle-wafer-templated epitaxial recrystallization of the a-Si layer. Regions exposed to the ATR process assume the orientation of the handle wafer while regions not exposed to the ATR process retain their original orientation. The practicality of this approach is d...

High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates

High performance 65-nm technology (Lpoly=45nm, EOT=1.2nm) bulk CMOS has been demonstrated for the first time on mixed orientation substrates formed by using direct silicon bonded (DSB) wafers and a solid phase epitaxy (SPE) process. The pFET performance is improved by 35% due to hole mobility enhancement on (110) surfaces as compared to (100) surfaces. nFETs on SPE-converted (100) surfaces exhibit the same performance as those on (100) controls. Ring oscillators fabricated using DSB with SPE show improvements of more than 20% compared with control CMOS on (100) surfaces

A study of trench-edge defect formation in (001) and (011) silicon recrystallized by solid phase epitaxy

Trench-edge defects formed during epitaxial recrystallization of trench-bounded amorphized silicon (a-Si) regions are examined as a function of Si substrate crystal orientation. In Si (001), rectilinear a-Si features having edges aligned with the crystal’s in-plane ⟨110⟩ directions recrystallize leaving trench-edge defects along all trench edges, whereas the identical features in Si (011) recrystallize without trench-edge defects along trench edges parallel to the crystal’s in-plane ⟨100⟩ direction and with trench-edge defects along trench edges parallel to the crystal’s in-plane ⟨110⟩ direction. The positions and lateral extent of these trench-edge defects suggest that their source is defective epitaxy on slow-growing {111} planes formed during recrystallization. A heuristic model proposed to explain the formation of these {111} planes correctly predicts the essentially defect-free recrystallization seen for rectilinear a-Si features in Si (001) having edges aligned with the crystal’s in-plane ⟨100⟩ dire...

Dual stress liner enhancement in hybrid orientation technology

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

Mask-edge defects in hybrid orientation direct-Si-bonded substrates recrystallized by solid phase epitaxy after patterned amorphization

Solid phase epitaxy (SPE) of patterned amorphized Si regions in direct-Si-bonded (DSB) hybrid orientation substrates is complicated by the fact that the amorphized Si regions being recrystallized have sides and bases formed from different Si crystals. In DSB wafers with a Si (011) DSB layer on a Si (001) handle wafer, the competition between lateral and vertical SPE produces distinctively angled mask-edge defects and recrystallization fronts. Some mask edges exhibit triangular bands of defective Si bounded by DSB and handle wafer {111} planes meeting at 90° angles, while other mask edges are relatively defect free, but can have downward-pointing facets of Si (011) growing below the DSB interface. A simple model recently developed to explain trench-edge defect formation and faceted recrystallization in bulk single-orientation Si appears to explain all of these observations.

Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances

Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overlap capacitance and the capacitance between the gate stack and metal contacts. These results are consistent with modeling. Although this is demonstrated with 65 nm devices, low-k spacers can cut active power consumption and have the potential to improve performance through reductions in parasitic capacitances which will be of greater importance for future technology nodes.

Scalability of Direct Silicon Bonded (DSB) Technology for 32nm Node and Beyond

When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.

Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates

Uniaxial strain relaxation of ultra-thin biaxial-tensile SSDOI is realized by ion-implant amorphization and solid phase epitaxy (II/SPE). The selective full amorphization in the thin SSDOI region, between raised source/drain (RSD) and channel, induces uniaxial strain relaxation in the channel. The SSDOI uniaxial strain relaxation enhances PFETs drive current by more than 20%

Higher hole mobility induced by twisted Direct Silicon Bonding (DSB)

Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (Lg= 2 mum), 10% higher at short channel (Lg = 36 nm) compared to (110) bulk PFETs. Moreover, we found that the thinner DSB shows better Vt roll-off characteristics. On the other hand, NFETs on DSB are as good as (100) bulk NFETs. Thin DSB substrate demonstrates 11% faster ring oscillator speed over thick DSB substrate and 30% faster over (100) bulk due to higher mobility and lower capacitance.