J. P. de Souza

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

Highly effective passivation of GaAs surface is achieved by a thin amorphous Si (a-Si) cap, deposited by plasma enhanced chemical vapor deposition method. Capacitance voltage measurements show that carrier accumulation or inversion layer is readily formed in response to an applied electrical field when GaAs is passivated with a-Si. High performance inversion mode n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with an a-Si/high-k/metal gate stack. Drain current in saturation region of 220mA∕mm with a mobility of 885cm2∕Vs were obtained at a gate overdrive voltage of 3.25V in MOSFETs with 5μm gate length.

High-Performance

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}

We demonstrate that the crystal orientation of single-crystal silicon layers may be changed in selected areas from one orientation to another by an amorphization/templated recrystallization (ATR) process, and then introduce ATR as an alternative approach for fabricating planar hybrid orientation substrates with surface regions of (100)- and (110)-oriented Si. The ATR technique, applied to a starting substrate comprising a thin (50–200 nm) overlayer of (100) or (110) Si on a (110) or (100) Si handle wafer, consists of two process steps: (i) Si+ or Ge+ ion implantation to create an amorphous silicon (a-Si) layer extending from the top of the overlayer to a depth below the overlayer/handle wafer interface, and (ii) a thermal anneal to produce the handle-wafer-templated epitaxial recrystallization of the a-Si layer. Regions exposed to the ATR process assume the orientation of the handle wafer while regions not exposed to the ATR process retain their original orientation. The practicality of this approach is d...

-Channel MOSFETs With High-

High performance 65-nm technology (Lpoly=45nm, EOT=1.2nm) bulk CMOS has been demonstrated for the first time on mixed orientation substrates formed by using direct silicon bonded (DSB) wafers and a solid phase epitaxy (SPE) process. The pFET performance is improved by 35% due to hole mobility enhancement on (110) surfaces as compared to (100) surfaces. nFETs on SPE-converted (100) surfaces exhibit the same performance as those on (100) controls. Ring oscillators fabricated using DSB with SPE show improvements of more than 20% compared with control CMOS on (100) surfaces

\kappa

For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.

Gate Dielectrics and

Trench-edge defects formed during epitaxial recrystallization of trench-bounded amorphized silicon (a-Si) regions are examined as a function of Si substrate crystal orientation. In Si (001), rectilinear a-Si features having edges aligned with the crystal’s in-plane ⟨110⟩ directions recrystallize leaving trench-edge defects along all trench edges, whereas the identical features in Si (011) recrystallize without trench-edge defects along trench edges parallel to the crystal’s in-plane ⟨100⟩ direction and with trench-edge defects along trench edges parallel to the crystal’s in-plane ⟨110⟩ direction. The positions and lateral extent of these trench-edge defects suggest that their source is defective epitaxy on slow-growing {111} planes formed during recrystallization. A heuristic model proposed to explain the formation of these {111} planes correctly predicts the essentially defect-free recrystallization seen for rectilinear a-Si features in Si (001) having edges aligned with the crystal’s in-plane ⟨100⟩ dire...

\alpha

Sub-100 nm short-channel In0.7Ga0.3As MOSFETs are demonstrated for both depletion- and enhancement-mode devices. High current of 960 muA/mum and record transconductance of 793 muS/mum have been achieved. Scaling behavior is investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

-Si Passivation

It is demonstrated using rapid thermal annealing that the electrical activation of Si+‐implanted GaAs capped with a plasma‐enhanced chemical vapor deposited (PECVD) silicon nitride (SixNy) layer requires longer annealing times compared to capless annealing. The SIMS profiles of 2H from the GaAs samples onto which SixNy caps were deposited using deuterated ammonia showed that deuterium atoms diffuse readily into the implanted region during PECVD. The improvement in the electrical activation of the capped samples with annealing time correlates directly with decreasing concentration of the 2H in the GaAs. It is postulated that the H atoms diffusing into GaAs during PECVD are trapped by the implantation‐induced damage and the delay in electrical activation corresponds to the time required for the release of the trapped H.

Amorphization/templated recrystallization method for changing the orientation of single-crystal silicon: An alternative approach to hybrid orientation substrates

The outdiffusion of Be implanted into GaAs has been found to be identical after capless or capped (Si3N4 or SiO2 ) rapid thermal annealing (RTA) at 900–1000u2009°C and to depend on the Be dose and its proximity to the surface. The outdiffusion is more pronounced when the Be implant is shallow ( 1×1015 cm−2 ). It is demonstrated that the Be outdiffusion is driven by the presence of a highly damaged surface layer. Auger results suggest the formation of a BeOx compound at the surface of a high‐dose (1×1016 cm−2 ) Be‐implanted sample that underwent capless RTA at 1000u2009°C/1 s. It appears that BeOx formation occurs when the outdiffused Be interacts with the native Ga/As oxides during annealing. All the Be remaining in the GaAs after a >900u2009°C/2 s RTA is electrically active.

High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates

We demonstrate self-aligned fully-depleted III-V MOSFETs using CMOS-compatible device structures and manufacturable process flows. Processes with good manufacturability and scalability, such as, gate definition and spacer formation using RIE, and formation of self-aligned source/drain extensions (SDE) and self-aligned raised source/drain (RSD), have been established on III-Vs. We demonstrate short-channel devices down to gate length LG = 30 nm. Our best short-channel devices exhibit peak saturation transconductance GMSAT = 1140 μS/μm at LG = 60 nm and supply voltage VDD = 0.5 V.