Conor O'sullivan | Researchain

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Featured researches published by Conor O'sullivan.

Archive | 2015

Opportunistic placement of ic test structures and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product ic chips containing same

Indranil De; Dennis Ciplickas; Stephen Lam; Jonathan Haigh; Vyacheslav Rovner; Christopher Hess; Tomasz Brozek; Andrezej J. Stroljwas; Kelvin Doong; John Kibarian; Sherry F. Lee; Kimon Michaels; Marcin Strojwas; Conor O'sullivan; Mehul Jain

Archive | 2016

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

Archive | 2018

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Archive | 2018

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Archive | 2017

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells

Archive | 2017

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens

Archive | 2017

Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells

Archive | 2017

Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells

Archive | 2016

Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Yih-Yuh Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-Che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg H. Weiland; Nobuharu Yokoyama

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