Vyacheslav Rovner

Exploring regular fabrics to optimize the performance-cost trade-off

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

Design methodology for IC manufacturability based on regular logic-bricks

Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns (Palusinski et al., 2001 and Strojwas, 2003) can provide significant advantages in terms of manufacturability and design cost (Pileggi et al., 2003). Various forms of gate and logic arrays have been recently proposed that can offer such pattern regularity to reduce design risk and costs. In this paper, we propose a full-mask-set design methodology which provides the same physical design coherence as a configurable array, but with area and other design benefits comparable to standard cell ASICs. This methodology is based on a set of simple logic primitives that are mapped to a set of logic bricks that are defined by a restrictive set of RET (resolution enhancement technique)-friendly geometry patterns. We propose a design methodology to explore trade-offs between the number of bricks and associated level of configurability versus the required silicon area. Results are shown to compare a design implemented with a small number of regular bricks to an implementation based on a full standard cell library in a 90nm CMOS technology.

Regular logic fabrics for a via patterned gate array (VPGA)

Standard-cell-based ASIC costs are increasing so rapidly that fewer products have the volume required to justify NRE costs. Consequently, more designs are relying on programmable devices, such as FPGAs, which have inferior power-delay performance. We propose to explore new regular logic fabrics that are customizable by a few via masks to provide implementation simplicity and NRE costs comparable to an FPGA, but with power-delay performance closer to an ASIC. This paper describes the design of lookup tables (LUTs) similar to those used in FPGAs, but restructured for via-patternability and performance. Results demonstrate power-delay performance comparable to complex-function standard cells, but inferior performance compared to simple logic gates. We compare several logic block designs based on our heterogeneous regular logic fabrics with those constructed using standard cells.

Simplify to Survive, prescriptive layouts ensure profitable scaling to 32nm and beyond

The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed. Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a 65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the integrated process-design co-optimization, is introduced.

OPC simplification and mask cost reduction using regular design fabrics

Cost and complexity associated with OPC and masks are rapidly increasing to the point that they could limit technology scaling in the future. This paper focuses on demonstrating the advantages of regular design fabrics for OPC simplification to enable scaling and minimize costs for technologies currently in volume production. The application of such a simplified OPC flow results in much smaller mask data volumes due to significantly fewer edges compared to the conventional designs and OPC flows. Moreover, the proposed approach enables reduced mask write times, hence lower mask costs. We compare OPC performance and complexity on standard cell designs to that of layouts on a regular design fabric. We first demonstrate advantages and limitations within an industrial model-based OPC solution. Then, a simplified rulebased OPC solution is discussed for the Metal 1 layer. This simplified OPC solution demonstrates a 70X run time improvement and an order of magnitude reduction in both the output edge count per unit shape and shot count per unit shape while maintaining the printabalility advantages of regular design fabrics. The simplified OPC also demonstrates a 50% reduction in mask-write time. Finally, the benefit of regular design fabrics for OPC simplification and mask cost reduction at a 32nm node is discussed.

Benchmarking diagnosis algorithms with a diverse set of IC deformations

Diagnosis algorithms for integrated circuits (ICs) are typically developed and evaluated using a limited number of logic-level models of defect behaviors. However, it is well-known that real IC defects exhibit behavior well outside these models. Consequently, the utility of IC diagnosis methodologies may be uncertain. A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects. Specifically, we have proposed a simple yet powerful strategy using a small circuit and a set of bounded deformations (i.e., defects) for measuring the effectiveness of diagnosis techniques. Evaluation of several simple and commercial diagnosis algorithms indicates that this form of diagnosis benchmarking is viable.

Enabling application-specific integrated circuits on limited pattern constructs

Implementing sub-22nm designs using a limited set of pattern constructs can eliminate hotspot risk and can control systematic variability. Pattern regularity can incur a cell-level density penalty that is minimized or eliminated by co-optimization with circuits. More importantly, design with a limited set of pattern constructs can remove the limitations imposed by complex design rules, thus facilitating flexible synthesis of logic and memory blocks in place of hard IP.

Design Methodology of Regular Logic Bricks for Robust Integrated Circuits

Regularity in IC design has been recognized as an effective means to combat variability in nanoscale technologies. One way to enforce design regularity is to implement ICs using a small library of regular logic bricks. In this paper we propose a methodology for the design and synthesis of such logic bricks. Since logic bricks are comprised of a limited set of logic primitives for manufacturability reasons, we propose a primitive-based direct mapping approach for generating optimized bricks that, in contrast to classical synthesis approaches, can provide direct control of implementation structures at abstract functional level based on the detection of natural decompositions that exist in the function. We demonstrate considerable improvement in the performance of logic bricks that are generated by the proposed method as compared with those produced by a commercial synthesis tool.

Enabling technology scaling with "in production" lithography processes

As the industry hits a road block with RETs that attempt to aggressively scale k1, we propose to extend the life of optical lithography by a complete co-optimization between circuit choices, layout patterns and lithography. We demonstrate that the judicious selection of a small number of layout patterns along with the appropriate circuit topologies would not only enable k1 relaxation but also efficient implementation of circuits. Additionally, in this paper, we discuss the use of regular design fabrics to extend the life of current generation lithography equipment. We will introduce the Front End of Line (FEOL) limited regular design fabric. The metal 1 patterns for this fabric are selected such that we can utilize a 1.2 NA 32nm metal 1 lithography process without any area penalty with respect to standard cells with conventional design rules, which require a 32nm metal 1 process with a rather unrealistic k1 of 0.35 while using a more advanced 1.35 NA tool. We also demonstrate simulation results on 2-dimensional layout patterns. The results suggest that smart selection of layout patterns can enable the extension of single exposure lithography to a 32nm production lithography process.

Economic assessment of lithography strategies for the 22nm technology node

The unavailability of extreme ultra violet lithography (EUVL) for mass production of the 22nm technology node has created a significant void for mainstream lithography solutions. To fill this void, alternate lithography solutions that were earlier deemed to be technically and economically infeasible, such as double patterning technologies (DPT), source mask optimization (SMO), massively parallel direct write ebeam (MEBM) and Interference assisted lithography (Intf), are being proposed, developed and adopted to ensure the timely deployment of the 22nm technology node. While several studies have been undertaken to estimate the lithography process costs for volume production with the aforementioned technologies, these studies have provided only a partial analysis since they have not taken into account the impact on design density and product yield. In this paper we use the cost-per-good-die metric in order to capture process costs as well as yield and design density. We have developed a framework that estimates the lithography cost-per-good-die for SRAM arrays and have applied it to evaluate the economical feasibility of the various lithography strategies under consideration for the 22nm technology node. Specifically, we compare the cost-per-good-die for different 32MB SRAM arrays, each optimized for a different lithography solution. Our analysis shows that the selection of the best lithography strategy is both layer and volume specific. The use of DPT solutions is recommended for Active and Contact layers. The use of Intf is recommended for layers such as Poly, Metals and Vias in the case of low volume products. For medium to high volume products the use of SMO is recommended for Poly, Metals and Vias. This paper provides quantifies of economic benefit of the proposed lithography strategy.