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Dive into the research topics where Kimon Michaels is active.

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Featured researches published by Kimon Michaels.


international symposium on semiconductor manufacturing | 1996

Analysis of mixed-signal manufacturability with statistical technology CAD (TCAD)

David A. Hanson; Ronald J. G. Goossens; Mark Redford; Jim McGinty; John Kibarian; Kimon Michaels

We have developed a methodology which combines technology CAD (TCAD) simulation with statistical analysis of empirical data to predict and control the manufacturability of IC fabrication processes. As a result, manufacturing tolerance or sigma-based models (also known as worst-case models) can be determined before a significant sample size of fabricated devices can be characterized. Early on in the development cycle, empirical data is collected, and models built from simulated data are refined. These revised models are used to determine process control limits, and optimize in-line and electrical test measurement (E-test) for maximum observability of variation. As the process is stabilized, further refined models are used to perform yield diagnosis and tolerance analysis of circuits. This methodology has been applied to a number of BJT and submicrometer CMOS processes to create predictive sigma-based models, modify the fabrication recipe to meet objective specifications as development proceeds, and finally use them to control the manufacturing line.


international electron devices meeting | 2009

Co-optimizing process development, layout and circuit design for cost-effective 22nm technology platform

Kimon Michaels

The economic and technological challenges of process development are threatening the timely availability of advanced nodes. Meanwhile design and product organizations are demanding the continued delivery of Moores law density scaling to justify node migration. Balancing the requirements of design with the capabilities and physical limitations of advanced processes will require capitalizing on opportunities for co-optimization between process development, layout and circuit design. In this presentation, we will examine the challenges and highlight the opportunities for achieving an economically feasible path to 22nm.


design automation conference | 2009

DFM: don't care or competitive weapon?

Mark Redford; Joseph Sawicki; Prasad Subramaniam; Cliff Hou; Yervant Zorian; Kimon Michaels

The external specifications of an IC (functions, clock rate, power consumption, etc.) determine the competitiveness of a product. To be successful and profitable in the IC business, designers need to “out-design” their competitors. Usually, Design-For-Manufacturing (DFM) is discussed as a yield improvement strategy, but what is the value of DFM from a competitive point of view? Can DFM gives designers a competitive lever by helping them decide how far to push a design without creating a manufacturing disaster? Can DFM be used to optimize designs rather than just identify hot spots?


Archive | 2006

System and method for product yield prediction

Brian E. Stine; Christopher Hess; John Kibarian; Kimon Michaels; Joseph C. Davis; Purnendu K. Mozumder; Sherry F. Lee; Larg Weiland; Dennis Ciplickas; David M. Stashower


Archive | 2015

Opportunistic placement of ic test structures and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product ic chips containing same

Indranil De; Dennis Ciplickas; Stephen Lam; Jonathan Haigh; Vyacheslav Rovner; Christopher Hess; Tomasz Brozek; Andrezej J. Stroljwas; Kelvin Doong; John Kibarian; Sherry F. Lee; Kimon Michaels; Marcin Strojwas; Conor O'sullivan; Mehul Jain


Archive | 2016

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama


Archive | 2018

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama


Archive | 2018

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama


Archive | 2018

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama


Archive | 2017

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

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