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Indranil De

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Archive | 2001

Robust Method for Fast and Accurate Simulation of Random Dopant Fluctuation-Induced Vth Variation in MOSFETs with Arbitrary Complex Doping Distribution

Indranil De; Andrei Shibkov; Sharad Saxena

We present a robust, fast, and accurate method for prediction of threshold voltage fluctuations induced by random placement of dopants in the MOSFETs. It is used to accurately predict the threshold voltage fluctuation for an analog transistor design. The method allows easy coupling to a process and device simulation framework, and, hence, evaluation of dopant induced threshold voltage fluctuation at the transistor design stage. The methodology is also used to compare the threshold voltage fluctuation in ultra-short channel devices having different profile architectures.

Archive | 2015

Opportunistic placement of ic test structures and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product ic chips containing same

Indranil De; Dennis Ciplickas; Stephen Lam; Jonathan Haigh; Vyacheslav Rovner; Christopher Hess; Tomasz Brozek; Andrezej J. Stroljwas; Kelvin Doong; John Kibarian; Sherry F. Lee; Kimon Michaels; Marcin Strojwas; Conor O'sullivan; Mehul Jain

Archive | 2016

E-beam inspection apparatus and method of using the same on various integrated circuit chips

Indranil De; Christopher Hess; Dennis Ciplickas

Archive | 2016

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2018

Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2017

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2017

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

Archive | 2017

Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells

Stephen Lam; Dennis Ciplickas; Tomasz Brozek; Jeremy Cheng; Simone Comensoli; Indranil De; Kelvin Doong; Hans Eisenmann; Timothy Fiscus; Jonathan Haigh; Christopher Hess; John Kibarian; Sherry Lee; Marci Liao; Sheng-che Lin; Hideki Matsuhashi; Kimon Michaels; Conor O'sullivan; Markus Rauscher; Vyacheslav Rovner; Andrzej J. Strojwas; Marcin Strojwas; Carl Taylor; Rakesh Vallishayee; Larg Weiland; Nobuharu Yokoyama

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Christopher Hess

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Dennis Ciplickas

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Conor O'sullivan

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John Kibarian

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Jonathan Haigh

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Kelvin Doong

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Kimon Michaels

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Marcin Strojwas

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Stephen Lam

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Tomasz Brozek

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