Jimmy Tarrillo

Dynamic partial reconfiguration manager

Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.

Neutron cross-section of N-modular redundancy technique in SRAM-based FPGAs

In this paper the fault-masking capability of N-modular redundancy systems synthesized into SRAM-based FPGAs is evaluated. In the proposed N-modular technique an original self-adaptive majority voter elects the outputs of the redundant modules. Experimentally evaluated neutron cross-section, area, and power consumption were analyzed for different numbers of redundant modules, ranging from 3 copies (standard TMR) up to 7 copies.

Analyzing the Effects of TID in an Embedded System Running in a Flash-Based FPGA

This work analyzes the behavior of a designed embedded system composed of microprocessor, memories and SpaceWire (SpW) links under Total Ionizing Dose (TID) synthesized into a commercial flash-based FPGA from Actel. Two tests were performed: one the FPGA is configured just once at the beginning of the irradiation and the other the FPGA is reconfigured every 5 krad (Si). Results evaluate power supply current (Icc), temperature, function operation and performance degradation.

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments

SRAM-based FPGAs are attractive to many high reliable applications at ground level due to its high density and configurability. However, due to its high sensitivity to neutroninduced soft errors, the FPGA configuration memory bits may suffer unexpected bit-flips and consequently critical errors may occur. To cope with this problem, authors have proposed several mitigation techniques, which must be verified under the presence of faults. Since ground-level radiation experiments are very costly, fault injection is a suitable method to verify mitigation techniques in early stages of development. In this work, we present a fault injector platform implemented in a FPGA commercial board able to inject multiple bit-flips in the configuration memory bits of SRAM-based FPGAs based on a fault database collected on radiation experiments. We show the accuracy of our proposed fault injection campaign compared to radiation test results. We compare the soft error rate of three designs under the accumulation of multiple faults.

Designing and analyzing a SpaceWire router IP for soft errors detection

SpaceWire (SpW) is a well know communication standard platform proposed by European Space Agency (ESA). Due to its inherent properties of fault-tolerant and high-throughput, it is extensively used in avionics and satellite applications. When more than two SpW nodes communicate, a SpW Router is used. Such routers can be implemented in ASICs or in programmable devices. In order to perform fault tolerance experiments and since was not possible to find an open source of SpW Router, in this paper we present an open VHDL implementation of this router. Simulation was performed in order to validate the system, and synthesis results for ASIC and FPGA are presented. Finally, in order to analyze the SpW router behavioral when soft errors happen, a fault injection campaign was implemented and results were presented.

Improving error detection capability of a SpaceWire router IP

In this paper, we present a SpaceWire router IP protected against soft errors by using design level fault tolerance techniques. In order to obtain a low overhead and high protection, a fault injection experiment was performance to evaluate the most susceptible functions in the protocol. Based in the results, fault detection techniques were implemented in RTL level just in the most critical elements. Final results show that the error detection capability of the proposed IP increases in more than 100% with minimal area and performance overhead. The IP targets ASIC or Flash-FPGA platforms.

Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applications

Triple Modular redundancy technique is mostly used to mask transient faults in circuits operating in dependable systems. The generalization of this technique (known as nMR) allows the use of more than three redundant copies of the circuit to increase the reliability under multiple faults. The main drawback of nMR is its high power consumption, which usually implies in n times the power consumption of a single circuit. In this work, we show that such affirmation is far for being true in case of embedding the entire redundant system into a single SRAM-based FPGA. We estimate power consumption in some case-study circuits protected by nMR in SRAM-based FPGAs and compare to a proposed model that estimates power consumption penalty. Results demonstrate that nMR can be implemented with low power overhead in FPGAs and therefore it is a suitable technique for most applications synthesized into this type of programmable devices that need to cope with massive multiple faults.

Power Analysis in nMR Systems in SRAM-Based FPGAs

Triple Modular redundancy technique is mostly used to mask transient faults in circuits operating in dependable systems. The generalization of this technique (known as nMR) allows the use of more than three redundant copies of the circuit to increase the reliability under multiple faults. The main drawback of nMR is its high power consumption, which usually implies in n times the power consumption of a single circuit. In this work, we present a mathematical model that predicts the power consumption overhead based on the power characteristics of the basic module. We estimate power consumption in some case-study circuits protected by nMR in a commercial SRAM-based FPGA and compare to a proposed model that estimates power consumption penalty. Results demonstrate that nMR can be implemented with low power overhead in FPGAs and therefore it is a suitable technique for most applications synthesized into this type of programmable devices that need to cope with massive multiple faults.

Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

Critical applications must rely on fault-tolerant systems in order to guarantee an error-free execution since the cost of a system fault can be paid in terms of millions of dollars or, even worse, in terms of human lives. In this context, Dynamic Partial Reconfiguration (DPR) enables a more optimized and reliable usage of state-of-the-art Xilinx SRAM-based Field Programmable Gate Arrays (FPGA) resources over space and time. DPR techniques make use of the Internal Configuration Access Port (ICAP), an internal FPGA interface that allows changing on the fly the functionality of a portion of its logic. Unfortunately, a standard DPR flow requires the use of at least a microprocessor (MicroBlaze, PowerPC or ARM), extra memories due to the microprocessor and several peripherals, which results in dense and complex designs that may be easily corrupted by radiation incidence. This chapter presents a generic DPR manager core that has been optimized to provide high reliability. Results are shown in terms of performance, resources utilization and fault tolerance capability, which reinforce its advantages over traditional solutions.

Hardware Managers with File System Support for Faster Dynamic Partial Reconfiguration

FPGA-based platforms allow implementing reconfigurable systems that can change functionality of portions of hardware at runtime. For this purpose, non-volatile, off-chip storage is required to hold the partial-configuration bitstreams that will be used for reconfiguration. Accessing such devices requires a high CPU usage or a dedicated hardware such as a Direct Memory Access (DMA) module, especially when reading from mass storage units using file systems. Relieving the processor from bitstreams acquisition and reconfiguration control promotes parallelism and better task scheduling. This paper presents a dedicated Intellectual Property (IP) block which efficiently retrieves bitstreams from a FAT16 formatted memory and independently performs partial reconfiguration at the highest possible speed. Three versions of the same module are proposed to enable the creation of systems capable of accessing the memory with different protocols and control units. The evaluation results show the advantages of our approach in terms of reconfiguration and reading speed, reduced area overhead, flexibility and ease of use.