D. Harmon

Thermal conductance of IC interconnects embedded in dielectrics

Accurate prediction of temperatures in metal wiring for integrated circuits is essential to the evaluation of electromigration reliability for high-frequency applications and electrical overload as well as for wafer-level die testing. Accurate prediction requires knowledge of the thermal conductivity of the surrounding dielectric and the heating effect of applied currents. Both quasi-analytical and numerical models for line heating as a function of applied current are presented for the case of lines fully embedded in a dielectric. Heat loss and current density at the melting point are projected as a function of linewidth, line thickness, underlying insulator thickness and insulator thermal conductivity. As intuitively expected, these projections indicate the allowed current density decreases with increasing linewidth, line thickness and insulator thickness, and also decreases as thermal conductivity decreases. Furthermore, the models are found to match heat loss measurements for isolated lines in SiO/sub 2/ and return a value of 1.07 W/m-/spl deg/K for the thermal conductivity of the oxide.

Ultra-thin Gate Dielectric Plasma Charging Damage in SOI Technology

It was previously demonstrated that SOI MOSFET devices are more robust with respect to plasma process charging damage than bulk MOSFET devices. In this work, charging damage to the gate dielectric of an SOI device is induced by attaching different-area interconnect antennas to the gate and the diffusion nodes, and/or by attaching identically configured, but widely separated antennas to the nodes

Investigation of Plasma Charging damage impact on device and gate dielectric reliability in 180nm SOI CMOS RF switch technology

The impact of charging damage from plasma processes on device and gate dielectric reliability is investigated for MOSFETs fabricated in an SOI CMOS RF Switch technology. Although results from voltage breakdown measurements do not reveal any indication of plasma damage, detrimental antenna effects are observed on the negative bias temperature instability (NBTI) and hot carrier device performance. With regard to NBTI in P-channel SOI MOSFETs in particular, relaxation experiments are carried out under various bias conditions. Recovery effects which are well known for intrinsic NBTI are also observed for the antenna devices, but are found to be reduced relative to that of control devices.

Thermal and electromigration challenges for advanced interconnects

The combination of low k dielectric material application and aggressive scaling in advanced interconnects creates new challenges for thermal and electromigration solutions. The complexity and difficulty are discussed for modeling and evaluating thermal and EM interactions in circuit designs. A few examples are given to show quantitatively the impact of different dielectric materials on maximum allowed current density and scaling in Cu lines.

SOI charging prevention: chip-level net tracing and diode protection

In this paper we show that the SOI FET is conductive during processing, and also that a FET shunted across the gate and source/drain of another transistor does in fact protect that device against charging damage.

Gate oxide damage and charging characterization in a 0.13 /spl mu/m, triple oxide (1.7/2.2/5.2nm) bulk technology

The authors present data from a 0.13 /spl mu/m technology, in which the thickest oxide is 5.2 nm and the thinnest 1.7 nm, with a 2.2 nm oxide provided simultaneously. Our results indicate that dielectric integrity is affected for the 2.2 nm oxide, threshold voltage shift is important only for the 5.2 nm oxide, but that the 1.7 nm oxide is virtually immune to charging damage by any measure applied here (threshold voltage, gate leakage, TDDB, SILC). Qualitatively similar results are obtained for NFETs and PFETs.

Charging Damage and Product Impact in a Bulk CMOS Technology

In this paper, we tabulate the characteristics of antennas in several real designs in a 180-nm technology, and show data indicating that the product is not as susceptible to charging damage as the test structures used to control the process line. The experiment consisted of evaluating a large (500 pieces) sample of parts with considerable process-induced antenna damage - and yet no measurable degradation in product performance, yield, or reliability was found