Wing L. Lai

Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides

In this paper, we present experimental evidence on the voltage-dependence of the voltage acceleration factors observed on ultrathin oxides from 5 nm down to /spl sim/1 nm over a wide range of voltages from /spl sim/2 V to 6 V. Two independent experimental approaches, area scaling method and long-term stress, are used to investigate this phenomenon. We show the exponential law with a constant voltage-acceleration factor violates the widely accepted fundamental breakdown property of Poisson random statistics while the voltage-dependent voltage acceleration described by an empirical power-law relation preserves this well-known property. The apparent thickness-dependence of voltage acceleration factors measured in different voltage ranges can be nicely understood and unified with these independent experimental results in the scenario of a voltage-driven breakdown. In the framework of the critical defect density and defect generation rate for charge-to-breakdown, we explore the possible explanation of increasing voltage acceleration factors at reduced voltage by assuming a geometric model for the critical defect density.

CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics

The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulators.

On the Weibull shape factor of intrinsic breakdown of dielectric films and its accurate experimental determination. Part II: experimental results and the effects of stress conditions

For pt. I see ibid., vol. 49, no. 12, p.2131 (2002).The Weibull slope measurement techniques described in Part I are used to determine Weibull slopes as function of thickness, voltage, and temperature. The effect of stress temperature and voltage on Weibull slopes is investigated over a wide range of voltage and temperatures for several different oxide thickness values. It was found that Weibull slopes show a strong thickness dependence while Weibull slopes are essentially independent of stress conditions such as voltages and temperature. The implications of the voltage-independent Weibull slope on voltage-dependent acceleration factors are discussed. In addition, the impact of electron injection polarity on Weibull slopes is studied in detail. To further advance understanding, we compare the measured Weibull slopes with different nitrogen incorporation processes under gate injection mode. It was found that for ultrathin oxides below 3 nm to the first order, the Weibull slopes are relatively insensitive to the nitrogen incorporation process for which we investigated. Finally, we discuss the validity of the stress-induced leakage current measurement as an experimental means to measure the critical defect density.

A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell

This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.

Statistics of competing post-breakdown failure modes in ultrathin MOS devices

The statistical analysis of the time elapsed from first oxide breakdown to device failure (residual time) reveals that the distinction between hard breakdown (HBD) and soft breakdown (SBD) is meaningful for ultrathin oxides down to 1 nm. It also shows that the growth of the HBD current is progressive. Thus, the HBD prevalence ratio picture of post-breakdown reliability is generalized to include the HBD progressiveness. Moreover, it is shown that the statistics of residual time cannot be quantitatively understood unless the SBD mode is considered to be unstable and to finally cause the device failure. As a consequence, a worst case criterion is used to combine these two failure modes (unstable SBD and progressive HBD) into a global post-breakdown cumulative failure function. This combined approach is shown to be a valuable tool to interpret a broad range of apparently dissimilar experimental results in devices with gate oxides ranging from 2.7 to 1 nm. The existence of two post-breakdown failure modes highly complicates the complete characterization of the post-breakdown relevant magnitudes and introduces extra difficulties for the reliable extrapolation of reliability data to operation conditions and low failure percentiles. It is found that ultrathin oxides as thin as 1 nm show essentially the same post-breakdown phenomena as oxides above 2 nm. However, unstable SBD is found to have a more severe impact on the failure of these ultrathin oxides.

Successive oxide breakdown statistics: correlation effects, reliability methodologies, and their limits

This paper deals with the statistics of successive oxide breakdown (BD) events in MOS devices. Correlation effects between these successive events are experimentally related to the statistics of BD current jumps, thus suggesting that they are related to lateral propagation of the BD path. The application of the successive BD theory to chip reliability assessment is discussed. Several failure criteria and the related reliability methodologies are considered and some of their limits are established.

Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin oxides

In this work, we resolved several seemingly conflicting experimental observations regarding temperature dependence of oxide breakdown in the context of change of voltage acceleration factors with reducing voltages. It is found that voltage acceleration factor is temperature dependent at a fixed voltage while voltage acceleration factors are temperature independent at a fixed TBD. We unequivocally demonstrated that strong temperature dependence of time(charge)to-breakdown, TBDðQBDÞ, observed on ultra-thin gate oxides (<5 nm) is not a thickness effect as previously suggested. It is a consequence of two experimental facts: (1) voltage-dependent voltage acceleration and (2) temperature-independent voltage acceleration at a fixed TBD window. For the first time, time-to-breakdown at low temperature of � 50 Ci s reported. It is found that Weibull slopes are insensitive to temperature variations using accurate area-scaling method. The stress-induced leakage current (SILC) was used as a measure of defect-generation rate and critical defect density to investigate its correlation with the directly measured breakdown data, QBDðTBDÞ. The comprehensive and statistical measurements of SILC at breakdown as a function of temperature are presented in detail for the first time. Based on these results, we conclude that SILC-based measurements cannot adequately explain the temperature dependence of oxide breakdown. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domains constructed from two important empirical relations based on comprehensive experimental database. 2002 Published by Elsevier Science Ltd.

Off-state mode TDDB reliability for ultra-thin gate oxides: New methodology and the impact of oxide thickness scaling

A simple and practical new methodology, a so-called voltage-splitting technique, is proposed for reliability evaluation of the off-state mode in ultra-thin gate oxides. By applying a negative voltage on the gate while the drain is biased at the operational voltage, we successfully resolve the difficulty associated with the unrealistic high drain-bias stress, which leads to the excessive damage to oxides in the overlap region. Using this technique, we have demonstrated that the normalized breakdown results of the off-state mode are compatible with those obtained in the inversion mode with proper account for edge-tunneling current and effective area. The impact of high drain-bias stress has been shown to be detrimental to oxide integrity due to the presence of additional degradation mechanisms. Our results indicate that off-state oxide reliability will become an increasingly important concern as oxide thickness is scaled down.

Critical reliability challenges in scaling SiO2-based dielectric to its limit

Abstract The limitations of silicon dioxide dielectric reliability for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is then interpreted. Experimental data over a wide range of oxide thickness, voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. Resolution of seemingly contradictory observations regarding the temperature dependence of oxide breakdown is provided by this work. On the basis of these results, a unified, global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon dioxide-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50 nm technology node using silicon-dioxide-based gate insulators.

Critical assessment of soft breakdown stability time and the implementation of new post-breakdown methodology for ultra-thin gate oxides [MOSFET]

The reliability margin seriously shrinks when gate oxide thickness is scaled below 2 nm. In this work we pursue a general picture of the breakdown in ultra-thin oxides by studying the statistics of the residual time, T/sub res/, defined as the time elapsed between the occurrence of the first breakdown (T/sub BD/) and the time of device failure. We have found that a classification of the breakdown events into SBD (soft breakdown) and HBD (hard breakdown) is still meaningful in oxides with thickness down to 1 nm, although both modes finally cause the transistor failure after a certain stress time. The obtained results have allowed us to develop a reliability methodology that includes, in a general framework, the device failure by three different processes: i) progressive HBD; ii) degradation of SBD into HBD and iii) superposition of several successive SBD events.