D. Yakimets

Vertical GAAFETs for the Ultimate CMOS Scaling

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.

Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moores Law. For the first time, the performance of two GAA device options- lateral FET (LFET) and vertical FET (VFET)-is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi-Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power.

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.

Vertical device architecture for 5nm and beyond: Device & circuit implications

Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.

Holisitic device exploration for 7nm node

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.

Lateral NWFET optimization for beyond 7nm nodes

In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must for lateral NWFETs in order to reduce device parasitic capacitance.

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. The device parasitics appear as most important performance limiters. Following a top-down approach, we find the design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and a design level solution consisting in fin depopulation. The efficiency of each solution depends on the balance between interconnect and device parasitics.

Lateral versus vertical gate-all-around FETs for beyond 7nm technologies

Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.

Limitations on Lateral Nanowire Scaling Beyond 7-nm Node

In this letter, we have studied the impact on lateral nanowire transistors (LNW) performance of reducing the wire diameter from 7 nm to 5 nm. As technology scaling continues, the LNW device size is scaled here for beyond 7-nm nodes. Reducing the NWs gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic is improved by reducing the wire diameter. DC and ring oscillator benchmark have been performed for different NW size for sub-7-nm node using TCAD-based compact models. Using the 5-nm-diameter-based LNW at the gate length of 10 nm around 8-mV/decade subthreshold slope improvement is observed as compared with the 7-nm-diameter LNW. This leads to the possibility of improved performances for the 5-nm-diameter-based device. The NW device, with 5-nm wire diameter and 10-nm gate length can provide some area gain. Although the 5-nm-diameter device increases channel confinement, due to the reduced drive current and increased parasitics, overall device speed is lagging behind the 7-nm diameter device.