D. Jang

Self-heating on bulk FinFET from 14nm down to 7nm node

Self-heating effects in scaled bulk FinFETs from 14nm to 7nm node are discussed based on 3D FEM simulations and experimental measurements. Following a typical 0.7x scaling, heat confinement is expected to increase by 20% in Si-channel FinFETs and by another 57% for strained Ge-channel. Reducing the drive current needed to reach target performance by reducing capacitances, and fin depopulation help mitigate self-heating effects. These thermal behaviors propagates to AC circuit benchmark, resulting in ~5% performance variation for high performance devices due to device scaling and increased number of fins.

Holisitic device exploration for 7nm node

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.

Scaling of BTI reliability in presence of time-zero variability

In this paper, we first outline the impact of Bias Temperature Instability (BTI) on the transistor threshold voltage as a function of time and the gate oxide field. Subsequently, the correlation between time-zero and time-dependent variability is described. A combined distribution encompassing both contributions with their relative weights is derived. Finally, circuit-level insights on the BTI impact are given based on case study simulations of Ring Oscillators (ROs) at commercial-grade 28nm planar and research-grade 14, 10, 7nm FinFET technology nodes for several FET channel materials (e.g. Si, SiGe, Ge, InGaAs).

Lateral NWFET optimization for beyond 7nm nodes

In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must for lateral NWFETs in order to reduce device parasitic capacitance.

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. The device parasitics appear as most important performance limiters. Following a top-down approach, we find the design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and a design level solution consisting in fin depopulation. The efficiency of each solution depends on the balance between interconnect and device parasitics.

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.

Impact of fin shape variability on device performance towards 10nm node

A transition from planar to FinFET brings additional variability sources from 3D channel structure. In this study, the impact of fin shape variability on device performance, especially from the view point of short channel effect control, is investigated with using Si-validated TCAD. This reveals that the width, height and taper angle of fin have significant impact on the electrostatics of the device. In addition, through the statistical Monte-Carlo simulations with compact model, the impact of fin shape variability is visualized in comparison with conventional device variability sources, i.e., gate length, work function, and equivalent oxide thickness. As a result, fin width and fin angle are found to be major variability source in addition to gate length. This indicates that the suppression of the process variability in fin width and fin angle is key to control device variability, especially in advanced node.

Limitations on Lateral Nanowire Scaling Beyond 7-nm Node

In this letter, we have studied the impact on lateral nanowire transistors (LNW) performance of reducing the wire diameter from 7 nm to 5 nm. As technology scaling continues, the LNW device size is scaled here for beyond 7-nm nodes. Reducing the NWs gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic is improved by reducing the wire diameter. DC and ring oscillator benchmark have been performed for different NW size for sub-7-nm node using TCAD-based compact models. Using the 5-nm-diameter-based LNW at the gate length of 10 nm around 8-mV/decade subthreshold slope improvement is observed as compared with the 7-nm-diameter LNW. This leads to the possibility of improved performances for the 5-nm-diameter-based device. The NW device, with 5-nm wire diameter and 10-nm gate length can provide some area gain. Although the 5-nm-diameter device increases channel confinement, due to the reduced drive current and increased parasitics, overall device speed is lagging behind the 7-nm diameter device.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

5nm: Has the time for a device change come?

As we scale further towards very advanced nodes where power becomes a primary metric for scaling the need to maintain leakage under control while having performance gains is paramount. This paper debates the advantages and disadvantages of possible transition from FinFET to nanowire for 5nm as the trade-off between subthreshold slope and device Idsat has to be made and between performance and energy consumption.