Da-Yuan Lee

Post-soft-breakdown characteristics of deep submicron NMOSFETs with ultrathin gate oxide

The impacts of soft-breakdown (SBD) on the characteristics of deep sub-micron NMOSFETs were investigated. It is shown that the BD location plays a crucial role in the post-BD switching function of the device. When BD occurs at the channel, the turn-on behavior of the drain current would not be significantly affected, which is in strong contrast to the case of ED at the drain, Nevertheless, significant increase in gate current is observed in the off-state when the gate voltage is more negative than -1 V. Its origin is identified to be due to the action of two parasitic bipolar transistors formed after SBD occurrence at the channel.

Breakdown Modes and Their Evolution in Ultrathin Gate Oxide

Post-breakdown current–voltage characteristics of metal-oxide-semiconductor (MOS) devices with an ultrathin gate oxide layer have been carefully studied. Several breakdown modes were identified. Specifically, it was found that the typical soft-breakdown mode induced in an oxide layer thinner than 3 nm is actually quite different from that in an oxide layer thicker than 3 nm. Based on these findings, we have also proposed a model to explain the evolution of different breakdown modes. The model takes into consideration the thermal runaway process at the breakdown moment, and is substantiated by a number of experimental findings. Impacts of each breakdown mode on device switching behavior are also discussed.

Impacts of hole trapping on the NBTI degradation and recovery in PMOS devices

In this paper, impacts of hole trapping on the negative bias temperature instability (NBTI) degradation and recovery in PMOS devices was investigated. Dual-gate p- and n-channel MOSFETs were fabricated using a standard CMOS twin-well technology.

Process and doping species dependence of negative-bias-temperature instability for P-channel MOSFETs

The effects of poly-Si gate doping type and species on the negative-bias-temperature instability (NBTI) of p-channel MOS transistors were investigated. We found that, by properly suppressing boron penetration through careful thermal budget, NBTI can be reduced by proper fluorine incorporation. In addition, we found that NBTI is larger for devices with PMA annealing, thus clearly identified the role of hydrogen passivation in NBTI.

New insights into breakdown modes and their evolution in ultra-thin gate oxide

By carefully analyzing post-breakdown current-voltage characteristics of MOS devices, it was found that the soft-breakdown mode typically induced in devices with oxide thinner than 3 nm is quite different from that with oxide thicker than 3 nm. Based on our findings, a unified model is proposed to explain the evolution of different breakdown modes. Impacts of each breakdown on the devices switching behavior are also discussed.

Effects of Process and Gate Doping Species on Negative- Bias-Temperature Instability of p-Channel MOSFETs

The effects of poly-Si gate duping type and species as well as thermal treatments on negative-bias-temperature instability (NBTI) of p-channel metal-oxidc-semiconductor field effect transistors (MOSFETs) were investigated. We found that devices with n + -poly-Si gale depict a smaller threshold voltage shift after bias-temperature stressing, compared to their p + -poly-Si-gated counterparts. By carefully controlling the thermal budget to suppress boron penetration. NBTI can be reduced by fluorine incorporation in p + -poly-Si-gated devices. Finally. NBTI is found to be aggravated in devices subjected to H 2 postmetal-annealing, highlighting the important role of hydrogen bonds.

Enhanced Negative-Bias-Temperature Instability of P-Channel Metal-Oxide-Semiconductor Transistors due to Plasma Charging Damage.

The effects of plasma charging on the negative-bias-temperature instability (NBTI) of p-channel metal-oxide-semiconductor (PMOS) transistors were explored in this work. It is clearly shown that the threshold voltage shift during bias-temperature stressing (BTS) could be enhanced by plasma charging damage. More importantly, we also found that electron trappings are aggravated by plasma charging, even on new devices with large antenna area ratios prior to BTS. Our charge pumping current measurements confirm that the interface-state density is increased for devices with large antennas, both before and after the BTS. This indicates, without ambiguity, that electron trapping is solely responsible for the observed low (in absolute value) threshold voltage in new devices with large antennas. Finally, it is proposed that the NBTI characterization can be used as a sensitive method for characterizing the antenna effects in devices with ultrathin gate oxide, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down.

Impacts of HF etching on ultra-thin core gate oxide integrity in dual gate oxide CMOS technology

In this paper, we investigate the effects of HF etching on the integrity of ultra-thin oxides in dual gate oxide (DGO) CMOS technologies. We found that both the HF concentration in the etching solution and the over etching (OE) time are important parameters that greatly affect the device performance and reliability. Our results indicate that, with a proper over etching period, using a concentrated HF solution results in better ultra-thin gate oxides in terms of reduced defect density, improved device performance and reliability, compared to using diluted HF solution. It is also found for the first time that negative-bias-temperature instability (NBTI) immunity for PMOSFETs is improved by using concentrated HF solutions.

Effects of plasma-induced damage to ultrathin (/spl les/1.5 nm) gate dielectric on equivalent oxide thickness downscaling using plasma nitridation process

Plasma nitridation was used to increase the dielectric constant of SiO/sub 2/ so that the equivalent oxide thickness (EOT) could be reduced. The effects of plasma-induced damage to ultrathin (/spl les/15 A) plasma-nitrided oxide (PNO) on EOT scaling were systematically investigated. The study showed that increasing nitrogen concentrations of PNO using aggressive plasma nitridation failed to reduce the EOT because the plasma-induced parasitic oxidation resulted in a substantial increase in oxide thickness that overrode the dielectric constant increase and consequently increased the EOT. The carrier mobility degradations and higher HF etching rates of PNO demonstrated the damage from plasma nitridation. Although reducing base oxide thickness was able to scale down EOT, the efficiency was extremely poor; a decrease of 1.5 A in base oxide thickness only resulted in 0.3 A of EOT reduction. MOSFET device data and SIMS depth profiles indicated that a thinner base oxide was more susceptible to plasma-induced damage. Finally, this study showed that after optimization, the plasma nitridation process was able to reduce plasma-induced damage so that the EOT could be scaled down without penalties.

New Mechanism for Negative-Bias-Temperature Instability and Its Impact on Scaling of pMOSFETs

Abstract Negative-bias-temperature instability (NBTI) of pMOSFETs with ultra-thin gate dielectric is characterized. A new mechanism due to trapping of holes in the nitride/oxide (N/O) stack during bias-temperature stressing (BTS) was identified. Threshold voltage (Vth) shift caused by BTS was found to recover after BTS stressing. Such mechanism becomes more significant as channel length is scaled down, and could be important for future high-k gate dielectric applications.