Y.J. Song

Highly manufacturable high density phase change memory of 64Mb and beyond

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.

Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology

Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC

Highly reliable 50nm contact cell technology for 256Mb PRAM

Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10/spl mu/m CMOS technology.

Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90 nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 108 cycles, respectively. In addition, they are non-destructively readable above 107 read pulses at 100 ns and 1 uA.

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

PRAM cell technology and characterization in 20nm node size

We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.

A Novel nand Flash Memory With Asymmetric S/D Structure Using Fringe-Field-Induced Inversion Layer

A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and improve the th distribution is presented in this paper. The asymmetric S/D structure consists of a diffused junction and inversion layer which is induced by the fringe field of the gate bias voltage during NAND operation. To reduce the area overhead caused by the select transistors, a 64-cell NAND string, which is twice the number of cells used in conventional NAND devices, is also evaluated. The proposed NAND memory device is demonstrated by a 32-Mb test chip which is fabricated using a 60-nm NAND flash technology. It exhibits subthreshold slope characteristics that improved by 37% and a programmed th distribution width that improved by 35% while almost maintaining multiple-level-cell NAND flash performance requirements.

Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge2Sb2Te5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies

We developed FRAM embedded smartcard in which FRAM replace EEPROM and SRAM to improve the read/write cycle time and endurance of data memories in smartcard. Highly reliable sensing window for FRAM embedded smartcard was achieved by advanced integration technologies such as novel capacitor technology, multi-level encapsulating barrier layer (EBL) technology, and optimal inter-metallic dielectrics (IMD) technology.

A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs

Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and strong resistance to /spl alpha/-particle and cosmic ray irradiation. None of the available commercial memories meet all of the properties of the ferroelectric memory. Although ferroelectric memory has inherent good properties, full utilization of these properties has not yet been realized. Commercially available products are limited to low densities. The commercially available ferroelectric memory uses a 2T2C (two transistor-two capacitor) structure with single level metal instead of a 1T1C (one transistor-one capacitor) structure with multiple metal layers which is believed to be essential for mega-bit or giga-bit density memory. In this paper, an integration technology for high performance and high density FRAMs is developed using a 1T1C robust capacitor in a COB (capacitor over bit line) structure with triple metallization processes. The technology developed in this paper is evaluated with an experimental 4 Mb FRAM, which is the highest FRAM density developed to date.