Dong-won Shin

Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 /spl mu/m technology node and beyond

In this paper, a 0.15 /spl mu/m embedded DRAM technology is described which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-function gate with Si/sub 3/N/sub 4/ capped Ti polycide, and selective Co silicidation of source/drain diffusion by Si/sub 3/N/sub 4/ liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-aligned contact (SAC) etching. Low temperature Al/sub 2/O/sub 3/ stacked cell capacitor with hemispherical grain (HSG) makes it possible to realize the sufficient storage capacitance in DRAM arrays and the high performance transistor. The CMP planarization of interlayer dielectric enlarges the depth of focus for lithography and enables the multilevel metallization. These integration technologies can be fairly extendible to the future embedded DRAM in 0.13 /spl mu/m technology node and beyond.

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

A highly reliable 1T/1C ferroelectric memory

A reliable 1T/1C ferroelectric RAM has been successfully fabricated with 1.2 /spl mu/m conventional CMOS technology by adopting IrO/sub 2/ electrode and the Ti-rich PZT thin film. The Ti-rich PZT capacitor shows no degradation of sensing Pr after integration process. After 1/spl times/10/sup 10/ cycling, the loss of remnant polarization was less than 5%. In thermally accelerated (150/spl deg/C) test condition, more than 14 /spl mu/C/cm/sup 2/ for both data 0 and data 1 sensing Pr values are obtained even after 10 years.

The influence of IMD bake process on buried channel PMOS hot carrier reliability of advanced DRAM

We investigated the influence of the SOG deposition with two kinds of curing process on the hot carrier reliability of buried channel (BC) PMOSFET. It was found that the vacuum bake induced the effective negative charges in the trench sidewall oxide and degraded P+ active isolation and PMOS hot carrier reliability.

Improvement of metal photo process margin with OPC and CMP for 0.14 μm DRAM technology node and beyond

In this paper, we report highly effective Optical Proximity Correction (OPC) techniques to improve the process margin in the photo lithography process of metal layer, which can be applied to 0.14 micrometer DRAM technology node and beyond. The proposed test pattern reflects the optical limitation of each situation, the rules can be established by simply investigating the test patterns which solves the problems such as lack of contact overlap margin, line-end shortening, and size reduction in isolated and island patterns. This sophisticated rule is considering the vertical environment as well. Thanks to systematic sequence for rule extraction, we could minimize additional burdens such as error occurrence, rule set-up time, data volume, manufacturing time of mask. By applying this method, DOF margin of metal layer could be improved from 0.4 micrometer to beyond 0.6 micrometer, which provides sufficient process window for mass production of 0.14 micrometer DRAM technology. In addition, we also confirmed that the new OPC technology could be extended to the metal layer of 0.11 micrometer DRAM.