Daisuke Mizoguchi

A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.

A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme

An inductively coupled wireless interface achieves aggregated data rate of 195Gbit/s among 4 stacked chips in a package by arranging 195 transceivers in 50/spl mu/m pitch with power dissipation of 1.2W. The transmit power is controlled in accordance to the communication distance to reduce both the power dissipation and the crosstalk of the system.

Cross talk countermeasures in inductive inter-chip wireless superconnect

Inductive coupling among stacked chips in a package enables 1.2 Gb/s/channel data communications. An array arrangement of the channel increases data bandwidth, while the signal may be degraded by cross talk. In this paper, cross talk is measured and analyzed, and cross talk countermeasures are discussed for the first time. Received signal waveforms by the inductive coupling are measured by embedded voltage detectors on a test chip. The interference-to-signal ratio (ISR) has good agreement between the measurements and calculations from a theoretical model. It is found that cross talk is reduced to being negligibly small at a certain distance. If the channels are arranged at intervals of this distance, ISR is minimized. A technique based on time division multiple access (TDMA) is also proposed to further reduce cross talk.

Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35 /spl mu/m CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30 /spl mu/m in 90nm device generation, power dissipation will be 1mW/channel or bandwidth will be 1Tb/s/mm/sup 2/.

Measurement of inductive coupling in wireless superconnect

An inductive inter-chip wireless communication scheme in three-dimensional (3D) stacked chip has been reported to achieve high-speed, low-power, and low-cost inter-chip communication. In this scheme, inductive coupling becomes a fundamental of communication and it should be modeled to realize communication. In inter-chip communication, it is considered that eddy current effect and the reflection of electromagnetic field degrade transmission power. However, there is as yet no report on inter-chip inductive coupling showing these effects. In this study, the scattering parameter of inductive coupling in 3D stacked chip has been measured under three conditions. The first measurement is carried out by changing the inductance alignment vertically and horizontally to verify the estimation scheme of coupling coefficient. The second measurement is carried out to evaluate ground mesh effect on inductive coupling. The third measurement is carried out by changing bulk thickness with constant communication distance to evaluate eddy current effect in bulk. The results show that eddy current does not become a problem and power grid degrades communication efficiency.

Constant magnetic field scaling in inductive-coupling data link

A wireless transceiver utilizing inductive coupling has been proposed for communication between chips in system in a package. This transceiver can achieve high-speed communication by using two-dimensional channel arrays. To increase the total bandwidth in the channel arrays, the density of the transceiver should be improved, which means that the inductor size should be scaled down. This paper discusses the scaling theory based on a constant magnetic field rule. By decreasing the chip thickness with the process scaling of 1/α, the inductor size can be scaled to 1/α and the data rate can be increased by α. As a result, the number of aggregated channels can be increased by α2 and the aggregated data band-width can be increased by α3. The scaling theory is verified by simulations and experiments in 350, 250, 180, and 90nm CMOS.

Design of transceiver circuits for NRZ signaling in inductive inter-chip wireless superconnect

Recently, a 3-dimensional integrated circuits (3D-ICs) are appeared for high density packaging. High speed interconnection is expected in 3D-ICs. A wireless bus for stacked chips is presented in this paper. The interface utilizes inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero (NRZ) signaling were developed to reduce the power and achieve high data rate. Receiver circuits timing margin and sensitivity is discussed. Test chip was fabricated and timing margin was measured. The result agrees very well with simulation. Then crosstalk reduction techniques for channel array are proposed and its efficiency is demonstrated by test chip. The chip has 3/spl times/65 channel array, each channels performance is 1 Gbps, and maximum data rate of 195 Gbps are achieved by using proposed cross talk reduction techniques.