D. H. van Dorp

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L g down to 36nm

We report In_0.53GaAs-channel gate-all-around FETs with channel width down to 7nm and L_g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g_m by 25% compared to InAs S/D. A g_m of 1310 μS/μm with an SS_sat of 82mV/dec is achieved for an L_g=46nm device. At this L_g, a record I_on above 200μA/μm is obtained at I_off of 100nA/μm and V_ds=0.5V on a 300mm Si platform.