Darryl D. Restaino

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiN/sub x/, or SiC/sub x/N/sub y/H/sub z/ layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/. Activation energies for electromigration were found to be 2.0 eV, 1.4 eV, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/, respectively.

Atom motion of Cu and Co in Cu damascene lines with a CoWP cap

Electromigration of Cu and diffusion of Co in Cu damascene bamboo-like grain structure lines capped with CoWP have been studied for sample temperatures between 350 and 425 °C. Void growth from the Cu line/W via interface was observed. Bulk-like activation energy for electromigration of 2.4±0.2 eV was obtained for these samples suggesting that electromigration damage is greatly diminished for these on-chip Cu interconnections. The solubility and diffusivity of Co in Cu was determined from line resistance measurements of thermally annealed Cu lines which were affected by Co diffusion into the Cu line.

Interface engineering for high interfacial strength between SiCOH and porous SiCOH interconnect dielectrics and diffusion caps

The integration of low- and ultralow-k SiCOH dielectrics in the interconnect structures of very large scale integrated chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCNH diffusion cap and the SiCOH inter- and intralevel dielectrics (ILDs). It was observed that, due to the original deposition conditions, the interface layer was weakened both by a low adhesion strength between SiCNH and SiCOH and by the formation of an initial layer of SiCOH with reduced cohesive strength. The manufacturing process has been modified to engineer this interface and obtain interfacial strengths close to the cohesive strengths of the bulk ILDs. This paper discusses the causes for the original low interfacial strength and presents an approach for enhancing it by engineering the interface to the cap for both the dense SiCOH and porous SiC...

Channel cracking in low-k films on patterned multi-layers

This paper considers cracking of a low-k tensile film fabricated on top of a patterned multilayer. A finite element model has been established to study all the geometry effects of the top film and underlying layers. It is found that the driving force for film cracking, as calculated from the energy release rate, is greatly enhanced by the underlying layers of copper and low-k materials. The geometry dependence has been verified by a test structure. The results indicate that a low-k film that is intact when deposited on silicon may crack when integrated in a multilayer BEOL. IBM has successfully engineered a CVD SiCOH low-k film with reduced film stress and increased modulus without degrading the cohesive strength (or the dielectric constant). Accordingly, cracking of the film has been prevented even for the worst case interconnect structures.

Temperature dependence of the Al-fill processes for submicron-via structures

Today, numerous different PVD techniques are used for the filling of sub micron contacts and vias in ULSI devices. One of the most promising approaches is the Al-reflow process. In this process, voids in vias which form during the PVD deposition of Al are eliminated by the thermal diffusion of Al. The ability of the aluminum to diffuse into the voids becomes increasingly dependent on the temperature of the reflow steps as device dimensions decrease. Therefore, it becomes necessary to deposit the Al at high temperatures, with the risk to influence the electrical properties of other underlying metal films and roughen the metal surface due to larger grain sizes. In this paper, the effect of the Al-deposition temperature on contact/sheet resistance and short yield of the deposited film and the influence of high temperature Al depositions on the electrical properties of underneath lying metal stacks are investigated.

Development and optimization of porous pSiCOH interconnect dielectrics for 45 nm and beyond

A porous pSiCOH interconnect dielectric with a dielectric constant k=2.4 has been developed from mixtures of a SiCOH skeleton precursor and bicycloheptadiene (BCHD) and optimized for successful integration in the interconnect structure of 45 nm ULSI chip. The ulk pSiCOH is characterized by small pores, low pore connectivity, and excellent electrical properties. This paper describes the selection of the precursors, the optimization process and the properties of the optimized pSiCOH. The film has been qualified for integration in three 2X dual damascene metallization levels of 45 nm interconnects.

65nm Cu Integration and Interconnect Reliability in Low Stress K=2.75 SiCOH

A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep thermal cycle showed sensitivity to assembly which is controllable though chip edge structural engineering

Selective nickel and gold plating for enhanced wire bonding technology

Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record

Optimization of porous ultra low-κ dielectrics (κ ≤ 2.55) for 28nm generation

There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) performance, without de grading yield or reliability is through introduction of porous ultra low-κ materials (ULK) as interlevel dielectrics (ILD). This paper presents the ability to tune ULK films through simple processing optimization steps to meet the specific integration requirements. Balancing composition of the film to minimize damage needs to be coupled with improving mechanical integrity for packing compatibility.

Chip cracks during assembly: Finding and eliminating the critical defect

During the bond and assembly process of an organic module, the backside of the chip will be in tensile stress. Vertical cracking through the Silicon chip (as shown in Figure 1) can occur when the strength of the chip is lower than the stress that is applied through the bond and assembly processes and associated materials.