David L. Harmon

Voltage-dependent voltage-acceleration of oxide breakdown for ultra-thin oxides

We report the voltage-dependence of voltage acceleration for ultra-thin oxides from 2.2 V to 5 V over a range of T/sub ox/ values from 1.7 nm to 5.0 nm. This unique behavior manifest itself as a power-law voltage-dependence for time-to-breakdown (T/sub BD/) over a variety of experimental observations. Using the concept of energy-to-breakdown, we explore the possible scenarios such as fractional energy or defect generation probability as a function of voltage to account for the increase in voltage acceleration with decreasing voltages.

CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics

The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulators.

Interrelationship of voltage and temperature dependence of oxide breakdown for ultrathin oxides

We report that voltage acceleration of time- or charge-to-breakdown is insensitive to temperature variations over a wide range of temperature (30 to 200/spl deg/C) for oxides below 3 nm, regardless of oxide process, injection polarity or device type (NFET, PFET). Based on this observation, an essentially universal, non-Arrhenius temperature dependence for ultrathin oxide is obtained by a natural normalization scheme. The consequences of these findings for reliability projection are discussed.

New global insight in ultrathin oxide reliability using accurate experimental methodology and comprehensive database

In this paper, we critically examine several important experimental aspects concerning ultrathin oxide reliability. The statistical nature of breakdown measurements and the impact on data interpretation is discussed. Thickness dependence of Weibull slopes and its impact on reliability projection is reviewed. We also investigate the voltage-dependent voltage acceleration using two independent experimental methods over a wide range of oxide thickness values. Within the framework of a general defect generation model, we explore the possibility of a voltage-dependent defect generation rate to account for the increase in voltage acceleration with decreasing voltages. Using direct experimental results, we clarify that strong temperature dependence found on ultrathin oxides is a voltage effect, not a thickness effect as previously suggested, In the context of voltage-dependent voltage acceleration, we experimentally resolve various seemingly contradicting and confusing observations such as temperature-independent voltage acceleration and non-Arrhenius temperature dependence found on ultrathin oxides. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domain constructed from two important empirical principles based on comprehensive experimental database.

Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin oxides

In this work, we resolved several seemingly conflicting experimental observations regarding temperature dependence of oxide breakdown in the context of change of voltage acceleration factors with reducing voltages. It is found that voltage acceleration factor is temperature dependent at a fixed voltage while voltage acceleration factors are temperature independent at a fixed TBD. We unequivocally demonstrated that strong temperature dependence of time(charge)to-breakdown, TBDðQBDÞ, observed on ultra-thin gate oxides (<5 nm) is not a thickness effect as previously suggested. It is a consequence of two experimental facts: (1) voltage-dependent voltage acceleration and (2) temperature-independent voltage acceleration at a fixed TBD window. For the first time, time-to-breakdown at low temperature of � 50 Ci s reported. It is found that Weibull slopes are insensitive to temperature variations using accurate area-scaling method. The stress-induced leakage current (SILC) was used as a measure of defect-generation rate and critical defect density to investigate its correlation with the directly measured breakdown data, QBDðTBDÞ. The comprehensive and statistical measurements of SILC at breakdown as a function of temperature are presented in detail for the first time. Based on these results, we conclude that SILC-based measurements cannot adequately explain the temperature dependence of oxide breakdown. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domains constructed from two important empirical relations based on comprehensive experimental database. 2002 Published by Elsevier Science Ltd.

Critical reliability challenges in scaling SiO2-based dielectric to its limit

Abstract The limitations of silicon dioxide dielectric reliability for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is then interpreted. Experimental data over a wide range of oxide thickness, voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. Resolution of seemingly contradictory observations regarding the temperature dependence of oxide breakdown is provided by this work. On the basis of these results, a unified, global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon dioxide-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50 nm technology node using silicon-dioxide-based gate insulators.

Detection of thin oxide (3.5 nm) dielectric degradation due to charging damage by rapid-ramp breakdown

It is shown that the primary manifestation of charging damage in thin (<4 nm) oxides is a degradation of dielectric integrity, while the primary manifestation of damage in thick (>6 nm) oxides is a shift in threshold voltage or the degradation of hot-carrier immunity. It is therefore necessary to effectively monitor both dielectric integrity and the parametric shifts to measure all of the consequences of charging damage on a technology with gate oxide less than 4 nm. We demonstrate the efficacy of a ramp breakdown methodology for this purpose, showing that a simple measurement of current is not sufficiently sensitive, and that results equivalent to a lengthy time-to-breakdown test may be achieved. Furthermore, we show ramp data on some thousands of chips from a manufacturing line, which demonstrates robust charging behavior for realistic gate and wiring antennas.

Characterization and reliability of TaN thin film resistors

TAN resistors are commonly used in RFIC applications and are gaining acceptance in traditional CMOS designs. TAN materials, frequently used in fabrication of Cu interconnects can easily be applied to the fabrication of thin film resistors. Deposition and integration of the films may be well controlled to produce a high precision resistor, and the temperature coefficient of resistance (TCR) characteristics of the film make it ideally suited for application across a large temperature range. While the time zero characteristics of the device are well understood, of equal importance are the device reliability properties. In this paper traditional film characteristics such as resistance distributions and TCR characteristics are presented. A voltage ramp stress is employed to identify the critical current A constant voltage stress at high temperature is utilized for reliability evaluation. Based on the stress results, a reliability degradation model is derived to express the relationship between stress condition, resistance change, and lifetime. The results demonstrate that the TAN thin film resistor is reliable over traditional IC operating ranges. While TAN resistors are robust, application conditions of the resistor typically result in significant resistive joule heating. The joule heating effects on the resistor are included in the resistor degradation model. The effects of the joule heating on reliability for neighboring structures must also be considered. The effective result is that the maximum allowed use current of the resistor might be dictated by the resistive joule heating and not necessarily the resistor reliability itself. The effect of the joule heating on neighboring structures is a subject itself and will not be covered in this paper.

A comprehensive investigation of gate oxide breakdown of P+Poly/PFETs under inversion mode

Breakdown (BD) characteristics and electron transport across thin SiO₂ films has been thoroughly investigated for P+Poly-Si gate/PFET devices stressed under inversion mode. We resolve the anomalies in T_BD/Q_BD polarity dependence and shallower Weibull slopes commonly observed in PFET for T_OX>2nm. For thin oxides (1.8nm<T_OX<2.9nm), Q_BD data and Weibull slopes are found to be in excellent agreement with those of NFETs by considering valence-band electron tunneling. For ultra-thin oxides (T _OX<1.8nm), using an improved new BD detection methodology, the derived Q_BD results show reasonable agreement with those of thick oxides

Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation

Abstract It is shown that the primary manifestation of charging damage in thin ( 6 nm) oxides is a shift in threshold voltage and/or the degradation of hot-carrier immunity. It is therefore necessary to monitor both dielectric integrity and parametric shifts to determine the consequences of charging damage on a technology with multiple gate oxide thicknesses. We demonstrate the efficacy of a ramp breakdown methodology for measuring dielectric integrity, showing that a simple measurement of current is not sufficiently sensitive, and that results equivalent to a lengthy time-to-breakdown test may be achieved. We describe a highly accelerated hot-carrier stress for monitoring damage on thicker oxide and show how it illuminates latent damage and is superior to Fowler–Nordheim stressing for this purpose. Furthermore, we show data on some thousands of chips from a manufacturing line, which demonstrates robust charging behavior for realistic gate and wiring antennas.