Dierk Kaller

First- and second-level packaging of the z990 processor cage

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

Signal Integrity Verification of Multichip Links Using Passive Channel Macromodels

This paper presents a general strategy for the electrical performance and signal integrity assessment of electrically long multichip links. A black-box time-domain macromodel is first derived from tabulated frequency responses in scattering form. This model is structured as a combination of ideal delay terms with frequency-dependent rational coefficients. A new identification scheme is presented, which is based on an initial blind delay estimation process followed by a refinement loop based on an iterative delayed vector fitting process. Two alternative passivity enforcement schemes based on local perturbations are then presented. The result is an accurate and guaranteed passive delay-based macromodel, which is synthesized as a SPICE-compatible netlist for channel analysis. The proposed procedure enables safe and reliable circuit-based transient simulations of complex multichip links, including nonlinear drivers and receivers. The performance of the proposed flow is demonstrated on a large number of channel benchmarks.

Electronic packaging of the IBM System z196 enterprise-class server processor cage

In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Evolution of organic chip packaging technology for high speed applications

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and the recently introduced fine line core with micro vias, high signal input/output (I/O) applications and dense chip area array footprints can be supported. These technology improvements support specific new dense chip applications. In this paper the electrical characteristics and the evolution of this packaging technology is described. The electrical description is especially focussed on material characteristics and the signal integrity including cross talk. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multichip modules (MCM) are discussed. Also the power integrity is described on the basis of the results of a mid frequency power noise analysis.

Crosstalk analysis in high density connector via pin fields for digital backplane applications using a 12-port vector network analyzer

In this paper the authors present results from the crosstalk analysis of a high density single ended connector and its associated card via array obtained with 12-port vector network analyzer (VNA) measurements in the bandwidth from 10 MHz up to 20 GHz. The device under test used for this paper is typical for a high end mainframe processor node to node link scenario consisting of daughter cards plugged into a backplane card by using a multipin connector. In previous studies the authors have shown that mainly the connector via pin field is impacting the electrical link performance. Here, the measurements have shown that the via pin field constitutes a complex crosstalk problem depending on the orientation and the distance between victim and aggressor via, the common coupled via lengths, and the local power/ground environment.

Organic Chip Packaging Technology For High Speed Processor Applications

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the high dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported. In the present paper the electrical characteristics of the HDI organic chip packaging technology are described with regard to signal and power integrity. In addition different applications for single-chip and multi-chip modules are discussed

Electronic packaging of the IBM z13 processor drawer

IBM z13 processor drawer W. D. Becker H. Harrer A. Huber W. L. Brodsky R. Krabbenhoft M. A. Cracraft D. Kaller G. Edlund T. Strach The electronic packaging of the IBM z13i is the foundation for a processor drawer that provides a significant increase in processing power relative to the IBM zEnterpriseA EC12 (zEC12) system while managing power and cost to meet the z13 product objectives. The z13 system architecture differs from previous high-end z Systemsi designs due to the introduction of a drawer-based processor design, organic single-chip modules (SCMs) in place of the ceramic MCMs (multi-chip modules), and a cabled interconnect between drawers in place of the PCB (printed circuit board) backplane of the zEC12. These innovations are coupled with next-generation signaling interfaces, providing a significant increase in signal bandwidth. The next-generation voltage regulation and decoupling provides the efficient power delivery needed to build a new processor subsystem with 40% more processor cores than the zEC12. The memory bandwidth and capacity have more than tripled, and the input/output bandwidth of the processor chip doubled to provide excellent scalability at the processor socket, drawer, and system level. The electronic packaging has been designed to meet all of these challenges, and this paper presents the design and integration of the electronic packaging of the z13 system.

Packaging design challenges of the IBM system z10 enterprise class server

This paper describes the system packaging and technologies of the IBM System z10™ high-end Enterprise Class server. This machine exceeds the multiprocessor performance of the previous system by 50%. A new generation of the IBM Elastic Interface was developed in order to maintain the increased interconnect signal speed of up to 2.93 Gb/s. Power control and power delivery to the multicore processors were a special challenge for the server packaging because of the high currents and the high number of voltage domains.

Macromodel-Based Iterative Solvers for Simulation of High-Speed Links With Nonlinear Terminations

Data transmission on high-speed channels may be affected by several undesired effects, including coupling from nearby interconnects, dispersion, losses, signal reflections from terminations and from internal discontinuities, and nonlinear/dynamic effects of drivers and receivers. The latter are often neglected, leading to very fast solvers, whose results may, however, be questionable when driver/receiver nonlinearities are important. This paper presents a framework for the transient analysis of complex high-speed channels with arbitrary nonlinear termination circuits. The approach is based on decoupling channel and terminations through a scattering-based waveform relaxation (WR) formulation. The channels are here cast as delay-rational macromodels, which are solved in discrete time domain through fast delayed recursive convolutions. The terminations can be either arbitrary circuits, solved by SPICE, or nonlinear behavioral macromodels, which are here formulated in discrete-time scattering representations. To overcome the known convergence issues of standard WR methods, we apply here more general iterative solution schemes, such as generalized minimal residual and biconjugate gradient stabilized, integrated into inexact Newton iterations, obtaining a set of numerical schemes with guaranteed convergence. The excellent performance of the proposed approach is illustrated on a large set of benchmarks.

Novel organic chip packaging technology and impacts on high speed interfaces

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported. These technology improvements allow specific applications. In this paper the electrical characteristics of the HDI organic chip packaging technology are described with regard to signal and power noise. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multi-chip modules (MCM) are discussed.