Bernd Garben

Frequency dependencies of power noise

In this paper, frequency dependencies of delta-I noise caused by variations of the on-chip switching activity have been analyzed by simulations for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system. The switching frequency and the noise source waveform have been varied in case of a single delta-I step. For repeated delta-I steps the power noise dependencies on the repetition frequency, the duty cycle and the damping of the resonant loop have been analyzed. Simulations using switching current sources for on-chip switching have been confirmed by simulations with switching resistors plus de voltage source. Mid-frequency noise simulations using SPEED2000 and noise voltage measurements yield the same results within 6% for the first and second voltage droops and overshoots, if the real resistance of power/ground vias and module pins are included in the simulation.

First- and second-level packaging of the z990 processor cage

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements

This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The method allows fast and accurate power noise simulations with SPEED97 on highly complex packaging structures. Simulation results for the mid-frequency power noise amplitudes on module and board planes and dependencies on decoupling capacitor parameters are presented. The package model used for the simulations allow the identification of the dominant resonant oscillations on the power distribution system following a delta-I step and yield the time response of the on-chip, on-module and on-board decoupling capacitors. The simulation results have been confirmed by measurements within 5%.

Evolution of organic chip packaging technology for high speed applications

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and the recently introduced fine line core with micro vias, high signal input/output (I/O) applications and dense chip area array footprints can be supported. These technology improvements support specific new dense chip applications. In this paper the electrical characteristics and the evolution of this packaging technology is described. The electrical description is especially focussed on material characteristics and the signal integrity including cross talk. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multichip modules (MCM) are discussed. Also the power integrity is described on the basis of the results of a mid frequency power noise analysis.

Novel methodology for mid-frequency delta-I noise analysis of complex computer system boards and verification by measurements

This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The mid-frequency noise is caused by the current fluctuations of on-chip switching activity. The method provides very fast and efficient descriptions of highly complex packaging structures during every system development phase, which allows fast and accurate noise simulations with SPEED97. The simulation results have been confirmed by measurements to within 5%.

Organic Chip Packaging Technology For High Speed Processor Applications

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the high dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported. In the present paper the electrical characteristics of the HDI organic chip packaging technology are described with regard to signal and power integrity. In addition different applications for single-chip and multi-chip modules are discussed

Influence of damping and voltage dependent leakage resistance on mid-frequency power noise

Accurate predictions of power/ground-noise are essential for adequate chip and package design. This paper studies especially the influence of damping and leakage on the mid-frequency power noise caused by switching activity variations of logic circuits. The noise is determined by simulations and calculated by a closed form expression which is derived for a simplified 2D circuit representation of the chip and package power delivery network. Both approaches agree within 16%. The voltage dependency of the leakage resistance is found to be essential for the power noise when the noise is determined by the resonance between on-die capacitors and the next stage of decoupling capacitors. It is shown that damping and leakage reduce significantly the influence of the on-die decoupling capacitance and package capacitor inductance on the mid-frequency power noise.

Package and chip design optimization for mid-frequency power distribution decoupling

In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been analyzed. Conclusions are presented to optimize the chip and package design.

Novel organic chip packaging technology and impacts on high speed interfaces

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported. These technology improvements allow specific applications. In this paper the electrical characteristics of the HDI organic chip packaging technology are described with regard to signal and power noise. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multi-chip modules (MCM) are discussed.