Dinesh Arvindlal Badami

Reliability challenges for copper interconnects

Abstract In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low- k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.

Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio.

Electromigration challenges for advanced on-chip Cu interconnects

Abstract As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS

A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FETs threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is frequency independent, an observation that suggests that VT degradation under AC stress can be equivalently measured through the simpler DC stress/relax sequence. An AC BTI model is developed that accurately captures the critical BTI relaxation effect through the DC stress/relax predictions on duty cycle dependence. A Ring Oscillator (RO) circuit is used as a model verification vehicle. Excellent agreement is demonstrated between the frequency degradation measurements obtained with a newly developed Ultra-Fast On-The-Fly (OTF) measurement technique optimized for BTI and the AC BTI model based RO simulations.

Short line electromigration characteristics and their applications for circuit design

Technology scaling has led to severe electromigration degradation for advanced interconnects. Taking full advantage of the Blech effect benefit has become more and more important for circuit design to overcome this EM performance degradation. Due to the wide range of circuit design layout variations, understanding the EM characteristics of the short lines closely related to the real circuit and chip design applications is needed. In this study, EM characteristics of a wide range of different short line structures are investigated. These structures include simple short line segments, short line segments with branches and with passive passing lines on top, and long lines with only a short portion carrying current. Implications of these results to circuit and chip design are also discussed.

Stress voiding characteristics of Cu/low K interconnects under long term stresses

Stress migration has been treated as one of the major reliability concerns for advanced interconnects. Extensive studies and various semi-empirical models have been reported. However, most of these models were developed based on fairly short term (1000 hours or less) stress data. In this paper, we present long term stress results (up to 20,900 hours) on a wide range of layout geometries. The observed stress migration behaviors for different layouts can be classified into four types: I: voiding rate is predominately driven by chemical potential gradient, and it increases with temperature; II: voiding rate is dominated by the combination of stress and chemical potential gradients, and it reaches the peak at intermediate stress temperature; III: voiding behavior shows defect-like characteristics, with a portion of the samples showing open circuit failures; and IV: voiding rate is very low, virtually no resistance change is seen at all stress temperatures. We conclude that to thoroughly investigate stress voiding characteristics, long term stresses with a wide range of layout geometries are needed.

Correlation between I–V slope and TDDB voltage acceleration for Cu/low-k interconnects

In this paper, a correlation between the I–V slope at low fields and TDDB voltage acceleration is demonstrated for the first time, based on a wide range of data from 32nm to 130nm node hardware. The data supports the √E model, which is based on electron fluence (leakage current) driven, Cu catalyzed, low-k dielectric breakdown. Using this correlation, a fast wafer level screen method was also implemented for process improvement and TDDB reliability monitoring.

Technology Reliability Qualification of a 65nm CMOS Cu/Low-k BEOL Interconnect

During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for 65nm Cu/low-k interconnects is reported and various reliability issues associated with process integration and material optimization during initial development stage are discussed. Finally, we demonstrate that with careful process and materials optimization, a superior interconnect reliability performance at the 65nm technology node can be achieved for 300mm fabrication. The projected reliability lifetimes of TDDB, EM, and SM meet the most stringent reliability targets and criteria

Comprehensive investigations of CoWP metal-cap impacts on low-k TDDB for 32nm technology application

as the current-carrying capability of a copper line is reduced due to interconnect dimension shrinkage, self-aligned CoWP metal-cap has been reported to be helpful to improve degraded electromigration (EM) reliability. However, adoption of the metal cap in general further exacerbates the already problematic low-k dielectric TDDB reliability at 32nm and beyond. This paper provides a comprehensive study of CoWP metal-cap impacts on low-k TDDB for 32nm technology application. It was found that CoWP could induce a severe degradation of low-k TDDB if its process is not optimized, and its impacts on dense low-k and porous ultra low-k (ULK) dielectrics were different. An optimized CoWP process with the least defect density could lead to an acceptable TDDB performance as compared to the control for both dense low-k and porous ULK dielectrics, while showing substantial improvements in EM and stress migration (SM).

A case study of electromigration reliability: From design point to system operations

While great efforts have been made to counter the EM reliability degradation due to technology scaling, closer cooperation is needed among semiconductor fabricators, circuit/chip designers and system integrators to ensure final product reliability. This paper presents an example of systematic EM reliability evaluation from design point definition to chip design verification, to system characterization, and finally to EM reliability monitoring from in-field operations.