Jean E. Wynne

Copper contact metallization for 22 nm and beyond

We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate worlds smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.

Yield and Reliability of Cu Capped with CoWP using a Self-Activated Process

Via and metal resistance, capacitance, stress migration lifetime, and high voltage leakage are characterized for Cu interconnects capped with either CoWP or CoWP + SiN. The CoWP is formed by a self-activated process using DMAB as a reducing agent, providing a very uniform CoWP film. Low via resistance and high stress migration lifetime are observed, even for relatively thin CoWP films without an SiN cap. The leakage current at high fields (3.0 MV/cm) is actually lower with a CoWP cap compared to an SiN cap

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

Stress migration lifetime for Cu interconnects with CoWP-only cap

Stress migration lifetime is characterized for a CoWP-only cap process (i.e. no dielectric cap) and a CoWP + SiN cap process. For the CoWP-only process, the stress migration lifetime depends on the CoWP thickness. In order to achieve a long stress migration lifetime, the CoWP must be sufficiently thick to protect the Cu during the via etch and strip processes. The data suggests that CoWP removal is enhanced beneath partially landed vias, resulting in reduced stress migration lifetime.

Effect of CoWP cap thickness on via yield and reliability for Cu interconnects with CoWP-only cap process

Via resistance and stress migration lifetime were characterized for a CoWP-only cap process (i.e. no dielectric cap) and a CoWP+SiN cap process. For the CoWP-only process, the via resistance and stress migration lifetime depended on the CoWP thickness. In order to achieve a tightly distributed via resistance and long stress migration lifetime, the data suggests that the CoWP must be sufficiently thick to protect the Cu during the via etch and strip processes.