Kimball M. Watson

Current status and future trends of SiGe BiCMOS technology

The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier migration to advanced CMOS technology generations. Lateral and vertical scaling are used to achieve smaller and faster SiGe HBT devices with greatly increased current densities. Improving both the f/sub T/ and f/sub MAX/ will be a significant challenge as the collector and base dopant concentrations are increased. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. Capacitors and inductors are two very important passives that must improve with each generation. The trend toward increasing capacitance in polysilicon-insulator-silicon (MOSCAP), polysilicon-insulator-polysilicon (Poly-Poly), and metal-insulator-metal (MIM) capacitors is discussed. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers is counter to the requirements of high Q inductors, potentially requiring a custom last metallization layer.

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

This paper describes the combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFETs. Devices subjected to a 60-min, 400/spl deg/C, 10% deuterium/90% nitrogen anneal after silicidization show a 32/spl times/ improvement in hot-electron lifetime. These same devices are then passivated with a deuterated barrier-nitride layer formed using deuterated ammonia (ND/sub 3/) and conventional silane (SiH/sub 4/). Further deuterium anneals along with conventional contact and metal-level processes are used to integrate the devices. Hot-electron stressing and SIMS analysis performed at various points in the processing give insight to methods of retaining the beneficial effects of deuterium during subsequent thermal processing.

Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.

Electrical characteristics and reliability of UV transparent Si/sub 3/N/sub 4/ metal-insulator-metal (MIM) capacitors

In this paper, we discuss the electrical characteristics and reliability of UV transparent Si/sub 3/N/sub 4/ metal-insulator-metal (MIM) capacitors. We examine film thicknesses in the range of 55 to 25 nm with capacitance densities from 1.2 ff//spl mu/m/sup 2/ to 2.8 ff//spl mu/m/sup 2/, respectively, for single MIM capacitors. A new approach for projecting the dielectric reliability of these films extends the limits of maximum operating voltage. Accounting for temperature acceleration and area scaling, the projected lifetimes can be met for a wide range of operating conditions.

Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress

A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f/sub T/ and 100 GHz f/sub max/. Accelerated current stress up to as high as J/sub C/=34 mA//spl mu/m/sup 2/ was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interfacial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10/sup 6/ hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.