Dohyun Lee
Samsung
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Publication
Featured researches published by Dohyun Lee.
symposium on vlsi technology | 2003
T. Park; S. Choi; Dohyun Lee; Jae-yoon Yoo; Byeong-Chan Lee; Jin-Bum Kim; Choong-Ho Lee; K.K. Chi; Sug-hun Hong; S.J. Hynn; Yun-Seung Shin; Jungin Han; In-sung Park; U-In Chung; Joo Tae Moon; E. Yoon; Jong-Ho Lee
Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.
symposium on vlsi technology | 1996
Dohyun Lee; Kye-hee Yeom; Myoung-kwan Cho; N.S. Kang; Tae-Hun Shim
With W/TiN stack gate deposited at high temperature, excellent time-dependent dielectric breakdown (TDDB) characteristics of the gate oxide were obtained in MOS capacitors. In the case of negative gate bias where thin oxide reliability becomes critical, the TiN gate provides a much longer time to breakdown than that of n/sup +/-poly gate due to a larger barrier height and less F-N tunneling current. In spite of skipping the conventional reoxidation process, a breakdown field larger than 10 MV/cm could be obtained in MOS transistors by undercutting TiN with boiling H/sub 2/SO/sub 4/. With a double spacer and undercutting scheme, the short channel effect of NMOS and PMOS transistors could be suppressed up to L/sub gate//spl sim/0.3 /spl mu/m.
symposium on vlsi technology | 2010
Kwang Soo Seol; Hee-Soo Kang; Jae-Duk Lee; Hyun-Suk Kim; ByungKyu Cho; Dohyun Lee; Yong-lack Choi; Nok-Hyun Ju; Changmin Choi; Sung-Hoi Hur; Jung-Dal Choi; Chilhee Chung
A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.
symposium on vlsi technology | 1995
Dohyun Lee; Suk Ho Joo; G.H. Lee; Joo-Tae Moon; Tae-Hun Shim; Jung-Young Lee
W/TiN stack gate has been investigated as a new gate electrode in ULSI CMOSFETs. With the combination of low resistivity of W and Si-midgap workfunction of TiN, very low sheet resistance and the proper characteristics of both types of transistors could be obtained simultaneously. With the deposition of TiN film at high substrate temperature, the breakdown characteristics of gate oxide could be improved considerably. The proper condition of dry etching on this structure has been also obtained.
Journal of Applied Physics | 2017
Hong Jeon Kang; Jeong Hyun Moon; Wook Bahng; Suhyeong Lee; Hyun Woo Kim; Sang-Mo Koo; Dohyun Lee; Dongwha Lee; Hoon-Young Cho; Jaeyeong Heo; Hyeong Joon Kim
Trap levels play an important role in semiconductor power devices. The barrier height of a metal-semiconductor junction, one of the important factors of unipolar devices, is influenced by the trap levels at its interface, i.e., interface states. However, there has not been much research on the interface states of Schottky diodes yet. Here, we report newly found KI1, KI2, and KI3 interface states of 4H-SiC Schottky diodes. We observed their changes after the first deep-level transient spectroscopy measurements, in which temperature rises to 750 K, and discussed the origins of these changes by using X-ray photoelectron spectroscopy and scanning electron microscopy. The KI1 was related to oxygen and photoresist (PR) residue, the KI2 was related to oxygen, and the KI3 was related to the PR residue.
symposium on vlsi technology | 2003
Youn-Keun Kim; Jung-Chak Ahn; T. Park; Chang Bong Oh; K.T. Lee; Hee Sung Kang; Dohyun Lee; Y.G. Ko; K.S. Cheong; J.W. Jun; S.H. Liu; JongWon Kim; J.L. Nam; S.R. Ha; J.B. Park; S.A. Song; Kwang Pyuk Suh
The smallest high density embedded 0.78 /spl mu/m/sup 2/ 6T-SRAM cell for high performance 90 nm SoC applications was successively integrated by using leading edge technologies such as 193 nm ArF lithography, 1.2 nm gate oxide, 50 nm transistor and Cu dual damascene with low-K dielectric. Fully working for SRAM shows the SNM value above 200 mV. Device current of 870 /spl mu/A//spl mu/m and 390 /spl mu/A//spl mu/m for NMOS and PMOS respectively is achieved at 1.0 V operation. Reliability life time on hot carrier immunity shows more than 10 years.
Archive | 2013
Chang-Hyun Lee; Jung-Dal Choi; Dohyun Lee
Archive | 2011
Jae-Duk Lee; Albert Fayrushin; ByungKyu Cho; Jung-Dal Choi; Sung-Hoi Hur; Kwang Soo Seol; Dohyun Lee
Archive | 2016
Chang-Hyun Lee; Dohyun Lee; Youngwoo Park; Su Jin Ahn; Jae-Duk Lee
Archive | 2014
Jae-Duk Lee; Youngwoo Park; Jintaek Park; Dohyun Lee; Kohji Kanamori