Donald R. Bradbury

Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

A statistical metrology framework is used to identify systematic and random sources of interconnect structure (ILD thickness) variation. Electrical and physical measurements, TCAD simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve ILD thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative CMP process we find that die-level neighborhood interactions are comparable to die-level feature-dependent effects, and within each die, die-level variation is greater than wafer-level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.

Control of lateral epitaxial chemical vapor deposition of silicon over insulators

Single‐crystal silicon films have been grown over SiO2‐covered regions of a single‐crystal silicon wafer by lateral epitaxial chemical vapor deposition (CVD). Nucleation of polycrystalline silicon on the SiO2 is suppressed by adding HCl to the SiH4 deposition gas. Sequential variation of the HCl partial pressure during different stages of the deposition process controls the relative deposition rates of the [100] and [110] planes and, consequently, the shape of the laterally advancing growth fronts, allowing the fronts from opposite sides of the SiO2 region to join uniformly. A plane surface is obtained by increasing the HCl partial pressure after coalescence. A standard silicon CVD epitaxial reactor is used for the deposition.

Effect of Insulator Surface on Selective Deposition of CVD Tungsten Films

Tungsten films have been selectively deposited on exposed silicon surfaces using different insulators important in IC technology to inhibit nucleation on the surrounding regions. A quantitative comparison of the nucleation rates on different surfaces was obtained. Nuclei form more readily on nitrogen‐containing films than on silicon‐dioxide films. The presence of phosphorus on the surface tends to inhibit nucleation either when the phosphorus is added by a surface treatment after the insulator is formed or when it is incorporated during deposition of the insulator; however, the inhibiting effect appears to be greater in the latter case. These results show that proper choice of an insulator and its surface preparation immediately before tungsten deposition permit thicker selective tungsten layers to be formed without nucleation on the surrounding insulator surfaces.

Trench-isolated transistors in lateral CVD epitaxial silicon-on-insulator films

Completely dielectrically isolated, p-channel MOS transistors have been obtained by lateral chemical vapor deposition (CVD) epitaxial overgrowth of buried oxide layers and subsequent lateral isolation with refilled trenches. The transistor characteristics are similar to those in bulk control wafers. Isolation between the device island and the substrate is approximately 1012Ω.

A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical‐Mechanical Polishing

A statistical metrology framework is used to identify systematic and random sources of interlevel dielectric thickness variation. Electrical and physical measurements, technology computer-aided design simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve interlevel dielectric thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative chemical/mechanical polishing process, we find that die-level neighborhood interactions are comparable to die level feature dependent effects, and that within each die, die level variation is greater than wafer level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.

Selective CVD tungsten as an alternative to blanket tungsten for submicron plug applications on VLSI circuits

The authors discuss the major reasons and solutions for selectivity loss during selective tungsten deposition. By applying these solutions to the selective process the nucleation count on the dielectric can be reduced to less than 1 nuclei/cm/sup 2/. In addition, a novel process has been developed in most photoresist is used as a sacrificial layer and an antinucleation layer is used to reduce the tungsten nucleation count on the surface of the dielectric to 0 nuclei/cm/sup 2/. The chemistry involved in producing a low-resistance contact on 0.7- mu m-diameter contacts is also discussed. Electrical test results showing contact resistance data on 0.7- mu m-diameter via chains with corresponding bridging data are presented.<<ETX>>

Low-resistance CVD W plug on Ti silicide for advance CMOS applications

Summary form only given. A novel approach is used to form a selective CVD (chemical-vapor-deposited) W plug on a Ti silicide surface by adding a nucleation layer in the contact hole. The technique is called SANIC (self-aligned nucleation layer formation in the contact). The process sequences of SANIC are described and the process latitude of the SANIC technique is examined. The SANIC process has been demonstrated on 1- mu m (drawn) CMOS SRAM and ring oscillators. The CMOS device characteristics and the corresponding gate delays of ring oscillators are shown.<<ETX>>