Doreen M. Y. Lai

Nickel-Silicide:Carbon Contact Technology for N-Channel MOSFETs With Silicon–Carbon Source/Drain

To explore the potential of nickel-silicide:carbon (NiSi:C) as contact technology for MOSFETs with silicon-carbon (Si:C) source/drain (S/D) regions, we examined the effects of incorporating 1.0 at.% of carbon in Si prior to nickel silicidation. The addition of carbon was found to improve the morphological and phase stability of NiSi:C contacts. This is possibly due to the presence of carbon at the NiSi:C grain boundaries and NiSi:C/Si interface, which will modify the grain-boundary and interfacial energies. This will influence the kinetics of NiSi:C silicidation. In this letter, we have also demonstrated the first integration of NiSi:C contacts in MOSFETs with Si:C S/D regions. We further show that NiSi:C silicidation suppresses the formation of active deep-level defects, leading to superior n+/p junction characteristics.

Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si0.8Ge0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si0.8Ge0.2 S/D p-FETs. The I Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.

Metal-Gate Work Function Modulation Using Hafnium Alloys Obtained by the Interdiffusion of Thin Metallic Layers

Metal-gate work function Φ m modulation using Hf alloys was achieved by the interdiffusion of bilayer metallic films each with a thickness of less than or equal to 10 nm. For a bilayer stack comprising a Hf layer on a Ni layer, varying the Hf/Ni metal thickness ratio from 0 (single-layer Ni stack) to 1.4 achieved Φ m tunability from 4.74 to 4.2 eV after forming gas anneal (FGA) at 420°C. Interdiffusion in Hf/Pt stack and Pt/Pt-Hf stack was also explored, and the largest Φ m shift of -0.5 eV from single-layer Pt and Pt-Hf stack, respectively, was obtained after annealing at 700°C for 30 s. The observed Φ m shift correlated to the extent of metal interdiffusion and was found to be strongly dependent on the metal thickness and anneal temperature. The Hf/Pt stack was further employed to demonstrate Φ m tunability of thin interdiffused metal layers on HfO 2 and HfLaO x high-k gate dielectrics. Through process optimization, the interdiffusion of thin metallic layers allows precise dual-gate Φ m control for advanced transistors.

Nickel-Aluminum Alloy Silicides with High Aluminum Content for Contact Resistance Reduction and Integration in n-Channel Field-Effect Transistors

In this paper, we demonstrate the silicidation of Ni 1-x Al x alloy film with the highest Al concentration reported to date for reduced contact resistance (R con ) through process optimization. Successful formation of Ni 1-x Al x alloy silicide with the use of film that has an Al concentration as high as 51% is shown. The onset of agglomeration has been eliminated, and the silicide yields a 0.40 eV electron barrier height, which is one of the lowest reported for any nickel alloy film. Subsequently, the benefits of the film using the optimal annealing condition are further verified through an 18% saturation drive current IDsat enhancement in n-channel metal-oxide-semiconductor field-effect transistors with Ni 1-x Al x silicide compared to NiSi. In addition, this paper also elucidates the dependency of Ni 1-x Al x alloy silicide properties on Al concentration and the annealing conditions.

A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancement

We report for the first time a new process technology for boosting the Ge content in SiGe source/drain (S/D) stressors to increase strain and performance levels in p-FETs. By laser-induced local melting and inter-mixing of an amorphous Ge layer with an underlying Si0.8Ge0.2 S/D region, a graded SiGe S/D stressor is formed upon recrystallization. Peak Ge content in the graded SiGe S/D is doubled over the as-grown film. Raman analysis confirmed the retention of high S/D strain levels due to the rapid non-equilibrium recrystallization process. The new process technology developed here employs several simple additional steps, including amorphous Ge deposition and laser anneal (LA). For a p-FET with Ge enriched S/D, 21% and 12% IDsat enhancement at a fixed IOFF of 2times10-8 A/mum is observed over control p-FETs with Si0.8Ge0.2 S/D formed by RTA and LA, respectively.

Band edge NMOS work function for nickel fully-silicided (FUSI) gate obtained by the insertion of novel Y-, Tb-, and Yb-based interlayers

Nickel fully-silicided (FUSI) gate work function Phin, was successfully tuned for the first time by the insertion of novel yttrium-(Y) based, terbium-(Tb) based, or ytterbium-(Yb) based interlayer at the gate/dielectric interface. Band edge Ni-FUSI gate Phim, (4.01 -4.11 eV) were obtained in a gate-first process flow (950 or 1000degC anneal) by an inserted ultra-thin (~1 nm) interlayer on SiO2 dielectric. We further demonstrate that gate-first implementation of the interlayers in a NiSi/HfO2 gate stack can realize a low Phim, of ~4.28 eV without dopant incorporation or Ni-alloying. In addition, NiSi Phim, modulation between Si midgap and band edge could be achieved by varying the interlayer thickness or M-silicide phase.

Practical Solutions to Enhance EWF Tunability of Ni FUSI Gates on HfO2

X.P. Wang, J.J. Yang, H.Y. Yu, M.-F. Li, J.D. Chen, R.L. Xie, C.X. Zhu, A.Y. Du, P.C. Lim, Andy Lim, Y.Y. Mi, Doreen M.Y. Lai, W.Y. Loh, S. Biesemans, G.Q. Lo, D.-L. Kwong 1 SNDL, ECE Dept, National University of Singapore, Singapore 117576, mfli@fudan.edu.cn 2 Institute of Microelectronics, Singapore 117685, 3 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, 4 Dept. of Microelectronics, Fudan University, Shanghai, China 201203, 5 Institute of Material Research and Engineering, Singapore 117602.