Hoong-Shing Wong

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

We explore a novel integration approach that introduces valence-mending adsorbates such as sulfur (S) or selenium (Se) by ion implantation and prior to nickel silicidation for the effective reduction of contact resistance and Schottky barrier (SB) height at the NiSi/n-Si interface. While a low SB height of ~0.12 eV can be obtained for NiSi formed on S-implanted n-Si, the insertion of a 1000degC anneal prior to silicidation leads to S out-diffusion and loss of SB modulation effects. We demonstrate that Se-implanted Si does not suffer from Se outdiffusion even after a 1000degC anneal, and subsequent Ni silicidation formed an excellent ohmic contact with a low SB height of 0.13 eV. Se segregation at the NiSi/n-Si (100) interface occurred. Implantation of Se and its segregation at the NiSi/n-Si interface is a simple and promising approach for achieving reduced SB height and contact resistance in future high-performance n-channel field-effect transistors.

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

We report a new method of forming nickel silicide (NiSi) on n-Si with low contact resistance, which achieves a Schottky barrier height of as low as 0.074 eV. Antimony (Sb) and nickel were introduced simultaneously and annealed to form NiSi on n-Si (100). Sb dopant atoms were found to segregate at the NiSi/Si interface. The devices with Sb segregation show complete nickel monosilicide formation on n-Si (100) and a close-to-unity rectification ratio. The rectification ratio Rc is defined to be the ratio of the forward current to the reverse current, where the forward and reverse currents are measured using forward and reverse bias voltages, respectively, having the same magnitude of 0.5 V. This process is also compatible and easily integrated in a CMOS fabrication process flow.

Low Schottky barrier height for silicides on n-type Si (100) by interfacial selenium segregation during silicidation

The electron Schottky barrier height ΦBn modulation for NiSi and PtSi formed on selenium-implanted n-type Si (100) has been experimentally investigated. Selenium (Se) segregation is observed at the silicide/n-Si(100) interface during silicidation process. ΦBn of 83 and 120 meV were achieved for Se segregated NiSi and PtSi on n-Si (100) interfaces, respectively. Contrary to previously reported Fermi level depinning effect in monolayer Se-passivated n-Si (100), the low ΦBn achieved in this work points to metal silicide Fermi level pinning near to conduction band EC of n-Si (100).

Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance

Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.

Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon–Carbon Source/Drain Stressors

We explore a novel silicide contact technology for effective Schottky barrier height PhiBn and contact resistance reduction, which is compatible with an advanced silicon-carbon (Si1-xCx) source/drain (S/D) stressor technology. The new silicide contact technology incorporates selenium (Se) that is coimplanted with S/D dopants into the silicon-carbon S/D prior to nickel silicidation, leading to the segregation of Se at the NiSi:C/n-Si0.99 C0.01 interface and the achievement of excellent ohmic contact characteristics. We demonstrate that the Se-coimplantation process contributes to a 23% drive current enhancement in a strained silicon-on-insulator n-MOSFET. The enhancement is attributed to the decrease of external series resistance which is primarily due to the reduction of silicide contact resistance.

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si0.8Ge0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si0.8Ge0.2 S/D p-FETs. The I Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.

Strained Silicon Nanowire p-Channel FETs With Diamond-Like Carbon Liner Stressor

We report the first integration of a high-compressive-stress diamond-like carbon (DLC) liner stressor with gate-all-around Si nanowire p-channel field-effect transistor (FET). DLC liner stressors with thicknesses of ~ 20 and ~ 40 nm were formed on p-FETs to induce high compressive strain in the channel region. As compared with nanowire p-FETs without liner stressor, substantial enhancements in ION and saturation transconductance GMSat were observed on p-FETs with DLC liner stressors. A thicker DLC liner stressor leads to a larger performance enhancement.

Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With Silicon–Carbon Source/Drain

We report the integration of a novel selenium segregation (SeS) technology in the silicide contact of strained n-MOSFETs featuring silicon-carbon Si_0.99C_0.01 source/drain (S/D) stressors. SeS at the NiSi:C/n-Si_0.99 C_0.01 interface leads to the achievement of low Schottky barrier height and reduced silicide contact resistance <i>R</i> _CSD. At a fixed <i>I</i> _OFF of 100 nA/ mum, the improved silicide contact technology employing SeS contributed to a 20% drive current <i>I</i> _ON enhancement and 30% total series resistance <i>R</i> _Total reduction over control strained devices. The <i>R</i> _Total improvement is primarily due to the reduction of external series resistance <i>R</i> _EXT, which is due to a reduced <i>R</i> _CSD at the NiSi:C/n- Si_0.99C_0.01 interface. Comparable DIBL, <i>V</i> _Tsat and gate leakage density were observed for strained n-MOSFETs with or without the SeS. The impact of introducing Se in the embedded Si_0.99C_0.01 S/D stressor on tensile stress level in the channel region of strained n-MOSFET was also investigated.

Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF -state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V.