Shin-Puu Jeng

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

A self-aligned airgap interconnect scheme

A new air-gap interconnect scheme with no additional patterning step successfully resolves the issue of unlanded via, and provides good interconnect reliability and improved packaging margin. We demonstrate that the insertion of airgaps in a very low-k dielectric (k=2.5) reduces the RC value of a 0.07um/0.07um comb structure by ∼14%, which is equivalent to an effective dielectric constant about 2.2.

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

Orthotropic stress field induced by TSV and its impact on device performance

An orthotropic stress field was observed in the vicinity of the Cu-filled TSV on nominal (100) silicon substrate from both μRaman measured data and validated FEM result. The orthotropic elastic behavior of silicon in the (100) plane is believed to be the reason. The FEM model was further validated by the comparison with the measured electrical data, and used to predict the device performance shift under the influence of the TSV-induced stress. The performance shift pattern also showed an orthotropic pattern. This finding has profound implication on 3D silicon stacking design rule and system integration.

Electromigration study of micro bumps at Si/Si interface in 3DIC package for 28nm technology and beyond

This paper is a study of the electromigration (EM) effects of micro bumps at silicon-silicon interface in 3DIC package for 28nm technology and beyond. Two joint schemes were designed and fabricated: one of the schemes was the joining of Sn-capped Cu post to ENEPIG (Electroless-Nickel-Electroless-Palladium-Immersion-Gold) UBM (Under-Bump-Metallurgy) pad on silicon substrate; the other scheme was the joining of top Cu post to bottom Cu post that formed a symmetrical joint structure. In-situ resistance was monitored to study the situation of joint degradation. During the test, a progressive resistance change was observed, which differed from the test data of conventional C4 (Controlled Collapse Chip Connections) bumps under regular test condition. (The detail will be described in this paper.) The experimental results showed that the rapid resistance shifts of both micro bump schemes were due to the high current density and the fast Cu-Sn IMC (Inter Metallic Compound) formation.

Chip-packaging interaction in Cu/very low-k interconnect

Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.

A Self-Aligned Air Gap Interconnect Process

A self-aligned air gap interconnect structure with sidewall reinforcement is developed. The new structure lowers the capacitance of 0.09um/0.09um (w/s) metal wires by as much as 25%, and exhibits low leakage current. As compared to un-protected air gaps, the structure also greatly improves the electromigration resistance and the misalignment margin for unlanded vias. Furthermore, the sidewall protection layer strengthens the overall mechanical strength and increases the packaging reliability.

Lead-free flip chip solution for 40 nm extreme low-k interconnect system

Lead-free flip chip package production solution for 40 nm technology node with aggressive ELK interconnect scheme and tight bump pitch of 150 µm is demonstrated. The use of LF bump and ELK dielectric in a same electronic component poses severe technical challenges due to the pronounced chip-packaging interaction in the system. In this paper, we reviewed the fundamental treatments to enhance the LF bump reliability. New challenges associated with the introduction of ELK are discussed. A careful optimization of material and layer thickness for each constituent in the flip chip package is the key to mitigate the chip-package interactions and to enable LF in 40 nm ELK interconnect.

Challenges of Low Effective-K approaches for future Cu interconnect

Challenges of various Low Effective-K approaches, including homogeneous Low-K and Air-Gap, for next generation Cu/Low-K interconnect will be presented. For homogeneous Low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & plannarization due to introduction of fragile lower k (K≪2.4) insulator will be focused. For Air-Gap, various types of Air-Gaps will be reviewed from the points of cost, layout/designer, and new processes involved.