Nicolas L. Breil

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

As an attempt to considerably reduce the equivalent contact resistivity of Schottky junctions, this letter studies the integration of rare-earth silicides, known to feature the lowest Schottky barriers (SBs) to electrons, coupled with a dopant segregation based on arsenic (As+) implantation. Both erbium (Er) and ytterbium (Yb) have been considered in the implant-before-silicide (IBS) and implant-to-silicide flavors. It is shown that the two schemes coupled with a limited thermal budget (500degC) produce an SB below the target of 0.1 eV. The implementation of IBS arsenic-segregated YbSi1.8 junctions in an n-type SB-MOSFET is demonstrated for the first time resulting in a current-drive improvement of more than one decade over the dopant-free counterpart.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

Formation and microstructure of thin Ti silicide films for advanced technologies

We report on the solid-state reaction of thin PVD Ti films with in-situ doped Si & SiGe alloys using a combination of in-situ x-ray diffraction, sheet resistance, laser light scattering measurements and ex-situ x-ray pole figure analysis. Thin Ti films or thin bilayer films (Ni/Ti or NiPt/Ti) are found to be much more aligned with the underlying substrates. Millisecond laser anneals also lead to the introduction of strong in-plane texture.

Interface Study of SiO 2 / HfO 2 /SiO 2 Stacks Used as InterPoly Dielectric for Future Generations of Embedded Flash Memories

We have investigated the integration of Hf-based material as Inter Poly Dielectric in flash memories devices. Electrical measurements showed the good properties of SiO 2 /HfO 2 /SiO 2 stacks. We then interested to the impact of the thermal budget on this specific stack which induces changes in the electrical properties. XPS measurements suggests those changes are due to the presence of an Hf-silicate layer at the SiO 2 /HfO 2 interface.