Wolfgang Rösner

Planar and vertical double gate concepts

Abstract In this paper, we report a comparative study of different double gate architectures. The main focus is on the fabrication method of two different device concepts developed in our group. The first is a planar version with special SOI wafers or deposited films and the second is a vertical transistor with lithography independent channel length. In addition to a thorough structural analysis we present electrical characteristics of the fabricated devices.

20 nm tri-gate SONOS memory cells with multi-level operation

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.

50-nm vertical sidewall transistors with high channel doping concentrations

Vertical MOSFETs have been proposed in the roadmap of semiconductors as a candidate for sub 100 nm CMOS technologies. A process flow using sidewall gates and implantations instead of multiple layer depositions reduces process complexity and offers better CMOS compatibility. High doping concentrations in the channel are needed for sub 100 nm devices. Especially for vertical transistors the uniform channel doping is more critical than for a planar technology, where optimized profiles can be easier implemented. Therefore, we investigated for the first time vertical MOSFETs with high channel doping concentration up to 1*10/sup 19/ cm/sup -3/ and channel lengths down to 50 nm. The impact of the high doping levels on threshold voltage and on tunneling currents is discussed. Finally, by using slight process modifications first results on vertical double gate MOSFETs will be presented, which in principle can operate with an undoped channel region.

Multi-level p+ tri-gate SONOS NAND string arrays

Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found

Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

Abstract Drift-diffusion simulations have been carried out to investigate the design space for n-channel fully depleted (FD) SOI transistors with undoped channels and midgap gates in the 25–50 nm gate length regime. Gate length, Si-body thickness, source drain doping concentration profile, and spacer width have been varied. Provided that the gate length is larger than 3–4 times the Si-body thickness, we find that the high performance targets of the International Technology Roadmap for Semiconductors can be fulfilled for many different parameter combinations. This means that FD SOI is a suitable technology for devices with feature sizes on this length scale.

20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices

New device concepts have been introduced to overcome the problems of planar microelectronic devices. The FinFET, which is a variant of the double gate transistor concept, is a promising approach, requiring very fine lithography and etching processes. These steps have been implemented as process modules in a loop to standard production. An electron beam lithography system has been optimized for nano-patterning down to 20 nm with emphasis on feature size, overlay accuracy and automation. A four-step pattern transfer process with hard masks has also been developed using a high density plasma tool. Structures with steep side walls could be etched. The fin structures are imaged in TEM with direct and elemental mapping. The analysis of the side wall deposited during the etching process reveals that the etching is carbon free.

CMOS based arrays of nanogap devices for molecular electronics

In this paper we present a novel nanogap device architecture for molecular electronics which is fully CMOS compatible and non-invasive to the contacted self-assembled monolayer. The device exhibits precise control over the electrode spacing. Single cells as well as arrays with electrode distances of 2.5 nm have been realized and characterized in terms of basic functionality and yield. Simulations have revealed scalability for feature sizes down to the ten nanometer regime.

Full 3D Process and Device Simulation for FinFET optimization

Based on a state-of-the-art 3D process and device simulation framework, we present an extensive analysis of the impact of FinFET process parameters on the device characteristics. The results compare well with the available experimental data.

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

The leakage mechanisms in fully depleted (FD) SOI transistors with undoped channel are investigated. These devices - contrary to partially depleted devices - show a strong V/sub DS/ dependence of the leakage currents. Energy balance simulations, including band to band tunneling effects and impact ionization, have been carried out. Contrary to drift diffusion calculations, these simulations can account for the experimental data and show that the two effects can be separated. In order to reduce these leakage effects, the design of the drain has to be optimised.

Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics

Replacing oxide-nitride-oxide (ONO) dielectrics in charge trapping memories such as SONOS (silicon/ONO/silicon) and NROM (nitrided read only memory) by high-k materials potentially offers improved scaling properties of the devices. In particular, a high dielectric constant of at least one of the three layers allows one to reduce the total equivalent oxide thickness (EOT) thus achieving the same programming electric field as in ONO stacks at reduced voltage. In this study, we evaluate the retention time of charge trapping memories using Al/sub 2/O/sub 3/ as a trapping dielectric and as a control gate dielectric. We find sufficiently large shifts of the threshold voltage allowing for retention times of more than ten years for the Al/sub 2/O/sub 3/ charge trapping memories. High-temperature annealed, polycrystalline layers are found to be more useful than amorphous layers annealed at 400-600/spl deg/C due to better retention time, smaller EOT and flat band shifts and a smaller amount of fixed interface charges.