Lars Dreeskornfeld

20 nm tri-gate SONOS memory cells with multi-level operation

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.

Multi-level p+ tri-gate SONOS NAND string arrays

Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found

A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

We present for the first time the full integration scheme and 512 Mb product data for a trench DRAM technology targeting the 48 nm node. The key technology enablers are a new cell architecture wordline over bitline (WOB) realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery devices at reduced internal voltage, and the integration of a MIC/HfSiO trench capacitor.

Characterization of ultra-thin SOI transistors down to the 20 nm gate length regime with scanning spreading resistance microscopy (SSRM)

New device concepts have been introduced to fulfill the demands and scaling requirements of the International Technology Roadmap for Semiconductors (ITRS). This, in turn, increases the demands on the characterization methods, e.g. for the measurement of 2D-carrier profiles, which have to be improved to match. This article reports a comparative study of the electrical and analytical characterization of nanoscaled ultra-thin (UT) n-channel and p-channel SOI transistors. The devices were fabricated on 45 nm SOI with gate lengths as short as 20 nm. The gates were defined by electron-beam lithography and nanoscale dry etching. We use high resolution scanning spreading resistance microscopy (SSRM) to provide reliable information about the carrier profile and effective gate lengths of the devices. The results of these measurements are compared with electrical results and with high resolution TEM.