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Dive into the research topics where Eric S. Ainley is active.

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Featured researches published by Eric S. Ainley.


Microelectronic Engineering | 2002

Template fabrication schemes for step and flash imprint lithography

Todd C. Bailey; Douglas J. Resnick; David P. Mancini; Kevin J. Nordquist; William J. Dauksher; Eric S. Ainley; A. Talin; Kathy A. Gehoski; Jeffrey H. Baker; Byung Jin Choi; Stephen C. Johnson; Matthew E. Colburn; Mario J. Meissl; S. V. Sreenivasan; John G. Ekerdt; C. G. Willson

Abstract Step and flash imprint lithography (SFIL) is an attractive method for printing sub-100 nm geometries. Relative to other imprinting processes, SFIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. The purpose of this work is to investigate alternative processes for defining features on an SFIL template. The first method considered using a much thinner (


SPIE's 27th Annual International Symposium on Microlithography | 2002

High-resolution templates for step and flash imprint lithography

Douglas J. Resnick; William J. Dauksher; David P. Mancini; Kevin J. Nordquist; Eric S. Ainley; Kathleen A. Gehoski; Jeffrey H. Baker; Todd C. Bailey; Byung Jin Choi; Stephen C. Johnson; S. V. Sreenivasan; John G. Ekerdt; C. Grant Willson

Step and Flash Imprint Lithography (SFIL) is an attractive method for printing sub-100 nm geometries. Relative to other imprinting processes SFIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. In addition, the imprint process is performed at low pressures and room temperature, minimizing magnification and distortion errors. The purpose of this work was to investigate alternative methods for defining high resolution SFIL templates and study the limits of the SFIL process. Two methods for fabricating templates were considered. The first method used a very thin layer of Cr as a hard mask. The second fabrication scheme attempts to address some of the weaknesses associated with a solid glass substrate. Because there is no conductive layer on the final template, SEM and defect inspection are compromised. By incorporating a conductive and transparent layer of indium tin oxide (ITO) on the glass substrate, charging is suppressed during SEM inspection, and the transparent nature of the final template is not affected. Using ZEP-520 as the electron beam imaging resist, features as small as 20 nm were resolved on the templates. Features were also successfully imprinted using both types of templates.


Journal of Vacuum Science & Technology B | 2002

Hydrogen silsesquioxane for direct electron-beam patterning of step and flash imprint lithography templates

David P. Mancini; Kathy A. Gehoski; Eric S. Ainley; Kevin J. Nordquist; Douglas J. Resnick; Todd C. Bailey; S. V. Sreenivasan; John G. Ekerdt; C. G. Willson

The feasibility of using hydrogen silsesquioxane (HSQ) to directly pattern the relief layer of step and flash imprint lithography (SFIL) templates has been successfully demonstrated. HSQ is a spin-coatable oxide, which is capable of high resolution electron-beam lithography. Negative acting and nonchemically amplified, HSQ has moderate electron-beam sensitivity and excellent processing latitude. In this novel approach, 6 ×6 × 0.25 in.3 quartz photomask substrates are coated with a 60 nm indium tin oxide (ITO) charge dissipation layer and directly electron-beam written using a 100 nm film of HSQ. Direct patterning of an oxide relief layer eliminates the problems of critical dimension control associated with both chromium and oxide etches, both required processes of previous template fabrication schemes. Resolution of isolated and semidense lines of 30 nm has been demonstrated on imprinted wafers using this type of template. During this evaluation, a failure of the release layer to provide a durable nonstic...


Journal of Vacuum Science & Technology B | 2004

Image placement issues for ITO-based step and flash imprint lithography templates

Kevin J. Nordquist; Eric S. Ainley; David P. Mancini; William J. Dauksher; Kathy A. Gehoski; J. H. Baker; Douglas J. Resnick; Z. Masnyj; Pawitter J. S. Mangat

Step and flash imprint lithography (SFIL) is an attractive, low-cost method for printing sub-100 nm geometries. The imprint process is performed at low pressures and room temperature, which minimizes magnification and distortion errors. Since SFIL is a 1× lithography technology, the template will require precise image placement in order to meet overlay specifications for multiple level device fabrication. In order to simplify the template fabrication process and facilitate post fabrication scanning-electron-microscope-based inspection, an integrated charge dissipation layer, such as indium tin oxide (ITO), is desired that is transparent to the SFIL exposure wavelength. The use of low-stress dielectric films such as SiON for the image relief layer minimizes the pattern distortions (<9 nm, mean+3σ) that occur after the pattern transfer process. Although ITO uniformity was also significantly improved by switching the ITO deposition process to an MRC sputter deposition system, image placement results were adv...


Journal of Micro-nanolithography Mems and Moems | 2002

High resolution templates for step and flash imprint lithography

Douglas J. Resnick; William J. Dauksher; David P. Mancini; Kevin J. Nordquist; Eric S. Ainley; Kathy A. Gehoski; Jeffrey H. Baker; Todd C. Bailey; Byung Jin Choi; Stephen C. Johnson; S. V. Sreenivasan; John G. Ekerdt; C. G. Willson

Step and flash imprint lithography (SFIL) is an attractive method for printing sub-100 nm geometries. Relative to other imprinting processes SFIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. In addition, the imprint process is performed at low pressures and room temperature, minimizing magnification and distortion errors. The purpose of this work was to investigate alternative methods for defining high resolution SFIL templates and study the limits of the SFIL process. Two methods for fabricating templates were considered. The first method used a very thin (<20 nm) layer of Cr as a hard mask. The second fabrication scheme attempts to address some of the weaknesses associated with a solid glass substrate. Because there is no conductive layer on the final template, scanning electron microscopy (SEM) and defect inspection are compromised. By incorporating a conductive and transparent layer of indium tin oxide on the glass substrate, charging is suppressed during SEM inspection, and the transparent nature of the final template is not affected. Using ZEP-520 as the electron beam imaging resist, features as small as 20 nm were resolved on the templates. Features were also successfully imprinted using both types of templates.


Workshop on Nanostructure Science, Metrology, and Technology | 2002

New methods for fabricating step and Flash Imprint Lithography templates

Douglas J. Resnick; Todd C. Bailey; David P. Mancini; Kevin J. Nordquist; William J. Dauksher; Eric S. Ainley; A. Talin; Kathleen A. Gehoski; Jeffrey H. Baker; Byung Jin Choi; Stephen C. Johnson; Matthew E. Colburn; Mario J. Meissl; S. V. Sreenivasan; John G. Ekerdt; C. Grant Willson

Step and Flash Imprint Lithography (SFIL) is an attractive method for printing sub-100 nm geometries. Relative to other imprinting processes SFIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. The purpose of this work is to investigate alternative methods for defining features on an SFIL template. The first method used a much thinner (< 20 nm) layer of Cr as a hard mask. Thinner layers still suppress charging during e-beam exposure of the template, and have the advantage that CD losses encountered during the pattern transfer of the Cr are minimized. The second fabrication scheme addresses some of the weaknesses associated with a solid glass substrate. Because there is no conductive layer on the final template, SEM and defect inspection are compromised. By incorporating a conductive and transparent layer of indium tin oxide on the glass substrate, charging is suppressed during inspection, and the UV characteristics of the final template are not affected. Templates have been fabricated using the two methods described above. Features as small as 30 nm have been resolved on the templates. Sub-80 nm features were resolved on the first test wafer printed.


22nd Annual BACUS Symposium on Photomask Technology | 2002

Critical Dimension and Image Placement Issues for Step and Flash Imprint Lithography Templates

Kevin J. Nordquist; David P. Mancini; William J. Dauksher; Eric S. Ainley; Kathleen A. Gehoski; Douglas J. Resnick; Zorian S. Masnyj; Pawitter J. S. Mangat

Step and Flash Imprint Lithography (SFIL) is an attractive low-cost method for printing sub-100 nm geometries. Relative to other imprinting processes, SFIL has the advantage that the template is transparent thereby facilitating conventional overlay techniques. In addition, the imprint process is performed at low pressures and room temperature, which minimizes magnification and distortion errors. Since SFIL is a 1X lithography technique, the template masks will require very good layer-to-layer overlay accuracy for multiple level device fabrication. To fabricate a transparent SFIL template, processing techniques familiar to existing binary phase shift mask fabrication are utilized. However, in order to fabricate the sub-100 nm features necessary for SFIL templates, thinner resist and chromium are necessary. Initial resolution tests have resulted in features sizes down to ~20 nm with the non-chemically amplified resist, ZEP520. Template to template overlay of <15 nm (mean + 3σ) can be achieved if the template fabrication procedure consists of a single 1” template exposed in the center of a 6” × 6” × 0.25” quartz blank.


Proceedings of SPIE, the International Society for Optical Engineering | 2006

Defect inspection for imprint lithography using a die to database electron beam verification system

L. Jeff Myron; Ecron Thompson; Ian M. Mcmackin; Douglas J. Resnick; Tadashi Kitamura; Toshiaki Hasebe; Shinichi Nakazawa; Toshifumi Tokumoto; Eric S. Ainley; Kevin J. Nordquist; William J. Dauksher

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and Flash Imprint Lithography (S-FILTM) is a unique method for printing sub-100nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz. Three different experiments were performed. In the first study, large (350-400nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70nm. Using a pixel address of 3nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.


Microelectronic Engineering | 1999

Process optimization of a chemically amplified negative resist for electron beam exposure and mask making applications

Eric S. Ainley; Kevin J. Nordquist; Douglas J. Resnick; D.W. Carr; Richard C. Tiberio

NEB-22, a chemically amplified negative tone resist has been formulated by Sumitomo for e-beam lithography direct write and mask making applications. The resist has exhibited excellent characteristics which would also make it applicable for use in a SCALPEL exposure tool.^1^,^2 The initial processing results for Sumitomo NEB-22A5 material demonstrated extremely high resolution capabilities with excellent exposure latitude. Although the process worked well for many direct write and mask applications, improvements were needed to address SCALPEL concerns. The process was modified to maintain sensitivity and optimize resolution, exposure latitude and PEB latitude. Excellent results were obtained in a 200 nm film of NEB-22 with new process parameters.


Journal of Vacuum Science & Technology B | 1998

Comparison of negative resists for 100 nm electron-beam direct write and mask making applications

Kevin J. Nordquist; Douglas J. Resnick; Eric S. Ainley

A new negative tone, chemically amplified deep ultraviolet resist, Shipley UVN-2, and a negative electron-beam (e-beam) resist, Sumitomo NEB-22A5, have been investigated for use in direct write and mask fabrication applications. The Sumitomo NEB-22A5 material has shown superior high resolution capabilities with excellent exposure latitude for both isolated and line/space features. Line and space gratings and isolated lines of 100 nm were resolved in a 400 nm film of NEB-22 using a 40 kV e-beam exposure tool. UVN-2 resist has shown resolution down to 150 nm line/space features with excellent etch selectivity and postexposure bake critical dimension control. Both resists perform well with respect to delay stability before and after exposure. This article will discuss the process development of the two resists and compare the performance characteristics including resolution, exposure latitude, linearity, and etch selectivity in various chemistries. Effects relating to pre-exposure and postexposure bake delay...

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John G. Ekerdt

University of Texas at Austin

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S. V. Sreenivasan

University of Texas at Austin

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