Paul D. Agnello

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0

Silicides and local interconnections for high-performance VLSI applications

As the minimum VLSI feature size continues to scale down to the 0.1–0.2-µm regime, the need for low-resistance local interconnections will become increasingly critical. Although reduction in the MOSFET channel length will remain the dominant factor in achieving higher circuit performance, existing local interconnection materials will impose greater than acceptable performance limitations. We review the state-of-the-art salicide and polycide processes, with emphasis on work at IBM, and discuss the limitations that pertain to future implementations in high-performance VLSI circuit applications. A brief review of various silicide-based and tungsten-based approaches for forming local interconnections is presented, along with a more detailed description of a tungsten-based “damascene” local interconnection approach.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-/spl mu/m CMOS technology

This paper reports the experimental results of the first CMOS active pixel image sensors fabricated using a high-performance 1.8 V, 0.25 /spl mu/m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to enable CMOS as an image sensor technology.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.

A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell

This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.

A high-performance 0.08 μm CMOS

We demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (V/sub dd/<1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for L/sub eff/ down to 0.06 /spl mu/m in the NFET and 0.08 /spl mu/m in the PFET. Aggressive lateral and vertical dopant engineering allow the VT to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at V/sub dd/=1 V over the regular-V/sub T/ process.

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

High quality ultra-thin TM-SGOI substrate with T/sub SOI/ < 55 nm is developed to combine the device benefits of strained silicon and SOI. 80-90% Id,sat and electron mobility increase are shown in long channel nFET device. For the first time, 20-25% device performance enhancement is demonstrated at 55 nm short channel strained silicon SGOI nFET devices.

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I/sub off/ levels of 100 nA/um for 1.1 volt operation. The physical gate length (L/sub poly/) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I/sub off/ levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f/sub max/ of 193 GHz has been demonstrated along with an f/sub T/ of 178 GHz.