F. De Canio

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

65 nm CMOS analog front-end for pixel detectors at the HL-LHC

This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The paper thoroughly discusses the results, mainly focused on the charge sensitive amplifier, coming from the characterization of the submitted test structures.

An asynchronous front-end channel for pixel detectors at the HL-LHC experiment upgrades

A front-end channel prototype for pixel detectors has been designed for the upgrades of the HL-LHC experiments. The circuit is based on a Krummenacher feedback network to continuously reset the charge sensitive amplifier and on a fast threshold discriminator to implement a time-over-threshold (ToT) method and perform amplitude measurement. The circuit was developed in a 65 nm CMOS technology and takes an overall area not exceeding 25 μm×50 μm. The power dissipation per channel, not including dynamic consumption, is around 5 μW. This paper is in particular concerned with the characterization of the charge sensitive amplifier, whose gain and recovery time can be adjusted to comply with changes in the experiment parameters. A very small gain dispersion was detected in the set of characterized samples. An equivalent noise charge of 120 electrons was found for a detector emulating capacitance of 100 fF. The response of the amplifier is compatible with the speed requirements for the foreseen application.

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

This work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2 V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65 nm CMOS technology. Together with a conventional structure which exploits bipolar devices, a smaller solution based on pn diodes and a version with MOS transistors biased in weak inversion region are included. This paper intends to describe and compare the features of the different circuits designed.

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started.

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm2 and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35×35 μm2. ENC value is below 100 e− for an input capacitance of 50 fF and in-time threshold below 1000 e−. Leakage current compensation up to 50 nA with power consumption below 5 μW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DACs are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 μs. The total power consumption per pixel is below 5 μW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper.

Transmission lines implementation on HDI flex circuits for the CMS tracker upgrade

The upgrade of the CMS tracker at the HL-LHC relies on hybrid modules built on high density interconnecting flexible circuits. They contain several flip chip readout ASICs having high speed digital ports required for configuration and data readout, implemented as customized Scalable Low-Voltage Signalling (SLVS) differential pairs. This paper presents the connectivity requirements on the CMS tracker hybrids; it compares several transmission line implementations in terms of board area, achievable impedances and expected crosstalk. The properties obtained by means of simulations are compared with measurements made on a dedicated test circuit. The different transmission line implementations are also tested using a custom 65nm SLVS driver and receiver prototype ASIC.

A 65 nm Rad-Hard Bandgap Voltage Reference for LHC Environment

A radiation-hard BGR (bandgap voltage reference) circuit is here presented. Its able to maintain the output voltage accuracy over process, voltage, and temperature (PVT) variations, combined with extremely high total-ionizing-dose (up to 800 Mrad (SiO2)), as required by the next experiments upgrades of the Large Hadron Collider (LHC). The design has been dealt starting from several experimental results, collected from some testing devices, under radiation exposure. In particular, this information has been used modifying the model files provided by foundry, in order to consider the radiation exposure effects during the design process. Consequently, a rad-hard optimized sizing device has been devised. In addition, a particular layout solution has guaranteed a better radiation immunity for the temperature sensing elements (i.e., diodes). The bandgap reference circuit has been fabricated in a commercial 65 nm CMOS technology. Measurement results show a temperature coefficient of about 130 ppm/°C over a temperature range of 120 °C (from -40 °C to 80 °C, as required by application) and a variation of 0.3% for Vdd 1.08 V-1.32 V. The mean value of the BGR output is about 330 mV, with a 10% maximum shift when exposed up to 800 Mrad (SiO2). The power consumption is 240 μW at room temperature, with a core area of 0.018 mm2.

Low-power clock distribution circuits for the Macro Pixel ASIC

Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed, based on standard supply voltage and on auxiliary, reduced supply. Circuit performance, in terms of power consumption and speed, is evaluated for each of the proposed solutions and compared with that relevant to standard CMOS drivers.