Fabien Essely

Investigation of the Propagation Induced Pulse Broadening (PIPB) Effect on Single Event Transients in SOI and Bulk Inverter Chains

The propagation of single event transients (SET) is measured and modeled in SOI and bulk inverter chains. The propagation-induced pulse broadening (PIPB) effect is shown to determine the SET pulse width measured at the output of long chains of inverters after irradiation. Initially, narrow transients, less than 200 ps at the struck inverter, are progressively broadened into the nanosecond range. PIPB is induced by dynamic floating body effects (also called history effects) in SOI and bulk transistors, which depend on the bias state of the transistors before irradiation. Implications for SET hardness assurance, circuit modelling and hardening are discussed. Floating body and PIPB effects are usually not taken into account in circuit models, which can lead to large underestimation of SET sensitivity when using simulation techniques like fault injection in complex circuits.

A New Technique for SET Pulse Width Measurement in Chains of Inverters Using Pulsed Laser Irradiation

A new technique is developed to measure precisely and accurately the width of propagating voltage transients induced by irradiation of inverter chains. The technique is based on measurement of the supply current in a detection inverter, and permits a direct determination of the transient width with a 50 GHz bandwidth.

Investigation of Single-Event Transients in Linear Voltage Regulators

Single-event transients (SETs) from heavy ions and laser beam are investigated for two positive adjustable linear voltage regulators: the RH117 from linear technology and the HS-117RH from Intersil. Both positive and negative going transients are observed. The role of input voltage, load capacitance and supply current on the SET response is discussed.

Application of various optical techniques for ESD defect localization

Various optical defect localization techniques are applied on the same integrated circuits (IC). These circuits were previously stressed by Electro Static Discharges (ESD) to create defects. The results obtained by each technique were analyzed to determine the nature of the defects. The different data are compared to assess their sensitivity and to evaluate the contribution of each technique in a failure analysis flow.

Effect of physical defect on shmoos in CMOS DSM technologies

Abstract Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.

Optimizing Pulsed OBIC Technique for ESD Defect Localization

This paper presents a study of the well-known optical beam-induced current (OBIC) technique applied to electrostatic-discharge defect localization. The OBIC technique is improved by using a pulsed laser beam instead of a continuous one. Critical parameters of the experimentation are explored in this paper. We particularly discuss on the influence of the laser energy, the bias of the device under test and the spatial resolution of the technique.

Different failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure

The failure signatures of a grounded-base NPN bipolar ESD protection under multiple TLP and HBM stresses are analyzed. For this particular device having a graded collector region, multiple TLP or HBM stresses result in different types of defects. OBIC techniques and TCAD simulations are used to thoroughly analyze the involved physical mechanisms.

Scan-based ATPG diagnostic and optical techniques combination: A new approach to improve accuracy of defect isolation in functional logic failure

Nowadays, with the increasing complexity of new VLSI circuits, laser stimulation or emission techniques and scan-based ATPG diagnostic reach their limits in functional logic failure. To overcome these limitations, a new methodology has been established. This methodology, presented in this paper, combines the advantages of both approaches in order to improve accuracy of fault isolation and defect localization.

Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique

The optical IR-OBIRCh technique is a standard failure analysis tool used to localize defects that are located at interconnects layers levels. For a functional logic failure, a failing test pattern is used to condition the device into a particular logic state to generate the failure. Commonly, the defect is detected for a set of test patterns. All test patterns will not provide the same IR-OBIRCh response. A random selection of test patterns may not lead to localize the defect by IR-OBIRCh technique or give fake results. We have performed an extended study of IR-OBIRCh response of a functional logic failure in function of test patterns. Based on these results a best test pattern failure analysis flow has been developed and implemented in order to localize a functional logic failure with IR-OBIRCh technique.

Optimizing pulsed OBIC technique for ESD defect localization

This paper presents a study of the well-known optical beam-induced current (OBIC) technique applied to electrostatic-discharge defect localization. The OBIC technique is improved by using a pulsed laser beam instead of a continuous one. Critical parameters of the experimentation are explored in this paper. We particularly discuss on the influence of the laser energy, the bias of the device under test and the spatial resolution of the technique.