Chi-Nung Ni

Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

Laser anneal assisted contact resistivity reduction with post-silicide implantation for 14nm node and beyond

The continuing reduction of contact resistivity (ρC) is a critical challenge for device performance. In this paper the ρC reduction for n-SD (source/drain) is demonstrated using post-silicide implantation of Se or P into Ni(Pt) silicide, with various energies/doses and laser anneal conditions. The improvement of ρC is achieved without sacrificing junction integrity/leakage. Hence laser assisted post-silicide implantation can be a key enabler to realize low silicide contact for n-SD for the 14 nm node and beyond.

Schottky barrier height tuning using P+ DSS for NMOS contact resistance reduction

Nickel silicide (NiSi) contacts are adopted in advanced CMOS technology nodes as they demonstrate several benefits such as low resistivity, low Si consumption and formation temperature. But a disadvantage of NiSi contacts is that they exhibit high electron Schottky barrier height (SBH), which results in high contact resistance (Rc) and reduces the NMOS drive current. To reduce SBH for NMOS, we used phosphorous (P) ion implantation into NiPt silicide with optimized anneal in order to form dopant segregated Schottky (DSS). Electrical characterization was performed using test structures such as Transmission Line Model, Cross-Bridge Kelvin Resistor, Van der Pauw and diodes to extract Rc and understand the effects of P+ DSS on ΦBn tuning. Material characterization was performed using SIMS, SEM and TEM analysis. We report ∼45% reduction in Rc over reference sample by optimizing ion implantation and anneal conditions (spike RTA, milli-second laser anneals (DSA)).

NMOS contact engineering for CMOS scaling

The 10-7 nm CMOS nodes require that ρc be reduced to <; 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.

Selenium segregation optimization for 10 nm node contact resistivity

Contact resistivity (ρ_C) reduction for n-SD (source/drain) with Se⁺ implant was evaluated for different integration schemes. It is found that Se⁺ implant energy is one of the most critical process parameters for ρ_C improvement, achieved by placing the Se⁺ peak close to silicide (TiSi₂ or NiPtSi)/Si interface and minimized implant damage. Recovery of implant damage to silicide and n-SD region was achieved with millisecond laser anneal, while minimizing dopant deactivation. This work demonstrated a viable integration pathway to realize low ρ_C solution for n-SD for 10 nm node.

The effect of interfacial oxide and high-κ thickness on NMOS V th shift from plasma-induced damage

Different thicknesses of interfacial oxide and high-κ were used to study the effects of plasma-induced damage (PID) in NMOS transistors. The thickness of high-κ HfO₂ was varied from 15Å to 25Å. The thickness of the interfacial layer (IL) with N₂O/H₂ was also varied from 5Å to 10Å. The threshold voltage (V_th) shift was observed to be greater in the thinner oxide using the same plasma condition. There was no significant effect with different IL thickness between 5Å and 10Å.

Damage engineered Se implant for NMOS TiSi x contact resistivity reduction

Low specific contact resistivity (7E-9 Ohm.cm2) was achieved for contacts with TiSix to in-situ epitaxially doped Si:P n-SD regions by use of Se implantation prior to Ti deposition. The key to this achievement is the optimization of implant energy and dose, and use of millisecond laser anneal to heal the implant damage, while allowing sufficient inter-mixing of Ti, Si, Se and P atoms across a smooth TiSix/Si:P interface, to realize the SBH-lowering benefits of Se.