Miao Jin

Facile synthesis of bimetallic Ag/Ni core/sheath nanowires and their magnetic and electrical properties.

This paper describes a facile method for coating Ag nanowires with uniform, ferromagnetic sheaths made of polycrystalline Ni. A typical sample of these core/sheath nanowires had a saturation magnetization around 33 emu g(-1). We also demonstrated the use of this magnetic property to align the nanowires by simply placing a suspension of the nanowires on a substrate in a magnetic field and allowing the solvent to evaporate. The electrical conductivity of these core/sheath nanowires (2 × 10(3) S cm(-1)) was two orders of magnitude lower than that of bulk Ag (6.3 × 10(5) S cm(-1)) and Ni (1.4 × 10(5) S cm(-1)). This is likely caused by the transfer of electrons from the Ag core to the Ni sheath due to the difference in work function between the two metals. The electrons are expected to experience an increased resistance due to spin-dependent scattering caused by the randomized magnetic domains in the polycrystalline, ferromagnetic Ni sheath. Studies on the structural changes to the Ni coating over time under different storage conditions show that storage of the nanowires on a substrate under ambient conditions leads to very little Ni oxidation after 6 months. These Ag/Ni core/sheath nanowires show promise in areas such as electronics, spintronics, and displays.

Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Atomic scale observation and characterization of redox-induced interfacial layers in commercial Si thin film photovoltaics

Thermodynamics considerations and experimental evidence suggest that redox reactions occur at the interfaces between transparent conductive oxides (TCOs) and the active silicon layers in photovoltaic stacks, with potentially nefarious effects to device efficiency. The presence of interfacial layers of oxidized silicon and reduced metal is confirmed here with analytical depth profiling techniques in industrially produced Si thin film solar cells. Atomic-resolution scanning transmission electron microscopy and energy loss spectroscopy are used to show that the specific chemistry of the interface, the front TCO being Sn-rich while the back TCO is Zn-rich, has a strong influence on the size of the resulting interfacial layer. Furthermore, the morphology of the interface and the impact of annealing treatments are also studied, leading to suggestions for possible improvements of commercial device efficiency.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

Selective Epitaxial Germanium Growth on Silicon - Trench Fill and In Situ Doping

This paper presented the selective epitaxial germanium growth on silicon by trench filling and doping. The process operated in a reaction rate limited regime at a low temperature (350°C to 400°C) to ensure reasonable growth rate, decent surface morphology, and high dopant incorporation in Ge.

PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

Enabling Effective Work Function Tuning by RF-PVD Metal Oxide on High-k Gate Dielectric

RF-PVD was investigated as a metal oxide cap deposition process to tune the effective work function in a gate first flow for high-k metal gate stacks. Samples with an aluminum oxide cap layer showed a large flat band voltage shift at minimal equivalent oxide thickness increase by about 0.1 nm. It was confirmed that RF-PVD induced no additional charge damage. Extended RF-PVD process runs also promised a robust process for high-k metal gate device manufacturing.

Ultra-low (1.2×10 −9 Ωcm 2 ) p-Si 0.55 Ge 0.45 contact resistivity (ρ c ) using nanosecond laser anneal for 7nm nodes and beyond

The recent FinFET scaling for 10–7nm node has resulted in significantly reduced contact areas for source/drain regions, leading to high contact resistance (Rc) [1-3]. Hence, it has become extremely critical to reduce the contact resistivity (ρ<inf>c</inf>) to < 1×10⁻⁹Ω.cm². ρ<inf>c</inf> can be reduced by increasing the dopant concentration at the metal/semiconductor interface and by lowering the barrier height [4]. Several studies have reported improvements in NMOS ρ<inf>c</inf> for Ti-based contacts using highly doped Si:P epi and advanced implant and activation techniques [5, 6]. For TiSi<inf>2</inf> based contacts, the Schottky barrier height (SBH) for n-ype silicon is low; however, it is slightly higher for p type SiGe. Thus, there is a strong requirement to improve the PMOS ρ<inf>c</inf> when Ti based contacts are used for both NMOS and PMOS.