G. Boccardi

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this architecture is capable of achieving fT/fmax values of 295/425 GHz for an effective emitter area of 0.13times5 mum2. In this new process approach, which is fully CMOS compatible, the collector and base are grown in a single-step non-selective epitaxial process on top of pre-defined bipolar areas. This provides new opportunities for collector-base profile engineering. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial pedestal defines the intrinsic device and makes deep trench isolation redundant. We describe the major features of the integration scheme and show measured fT/fmax values of 300/220 GHz on the first fabricated devices with an effective emitter area of 0.13times5 mum2.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

Improved sidewall doping of extensions by AsH 3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs

We demonstrate a novel photoresist-compatible FinFET doping technique that combines the advantages of deposition and implantation. Energy and deposition thickness optimization for the Ion Assisted Deposition and Doping (IADD) process provides excellent doping of nMOS extensions, thus reducing external resistance REXT. On current ION is improved by 6-8% for LG of 26-30 nm and by 15% for LG of 20 nm, with better SCE and DIBL.

Low Frequency Noise Analysis for Post-Treatment of Replacement Metal Gate

Post-treatment of replacement metal gate is investigated for the device performance improvement of high- k last p-type bulk FinFET using post-deposition annealing (PDA) and SF6 plasma treatment. Compared with untreated HfO2 reference, post-high- k deposition PDA and SF6 plasma-treated devices show improved driving current and hole mobility. With the carrier number fluctuations with correlated mobility fluctuation model, ~3 times lower input gate referred noise is observed in PDA and SF6 plasma-treated devices compared with untreated FinFETs. Post-treatments suppress the trap density of high- k last FinFET. PDA reduces oxide bulk trap whereas SF6 plasma affects both interface and oxide bulk trap.

Improved Channel Hot-Carrier Reliability in

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high- k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG ~ VD/2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis.

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Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

-FinFETs With Replacement Metal Gate by a Nitrogen Postdeposition Anneal Process

We report In_0.53GaAs-channel gate-all-around FETs with channel width down to 7nm and L_g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g_m by 25% compared to InAs S/D. A g_m of 1310 μS/μm with an SS_sat of 82mV/dec is achieved for an L_g=46nm device. At this L_g, a record I_on above 200μA/μm is obtained at I_off of 100nA/μm and V_ds=0.5V on a 300mm Si platform.

Negative Bias Temperature Instability in p-FinFETs With 45

Abstract. Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

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We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (JG) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (Nit) down to narrower fin devices [fin width (WFin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |VT|, and substantially improved reliability behavior due to reduction of bulk defects.