H. Arimura

15nm-W FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET_INV-normalized G_M,SAT,INT of 6.7 nm.mS/μm, the Si_0.3Ge_0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

Low-Frequency Noise Characterization of GeO x Passivated Germanium MOSFETs

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeOx interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/fγ noise (γ~1) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility.

Low Frequency Noise Analysis for Post-Treatment of Replacement Metal Gate

Post-treatment of replacement metal gate is investigated for the device performance improvement of high- k last p-type bulk FinFET using post-deposition annealing (PDA) and SF6 plasma treatment. Compared with untreated HfO2 reference, post-high- k deposition PDA and SF6 plasma-treated devices show improved driving current and hole mobility. With the carrier number fluctuations with correlated mobility fluctuation model, ~3 times lower input gate referred noise is observed in PDA and SF6 plasma-treated devices compared with untreated FinFETs. Post-treatments suppress the trap density of high- k last FinFET. PDA reduces oxide bulk trap whereas SF6 plasma affects both interface and oxide bulk trap.

NBTI in Replacement Metal Gate SiGe core FinFETs: Impact of Ge concentration, fin width, fin rotation and interface passivation by high pressure anneals

We report a broad study of Negative Bias Temperature Instability (NBTI) in Replacement Metal Gate (RMG) SiGe core FinFETs, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks, which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits from a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Reduced NBTI is observed in narrow fins, thanks to a reduced oxide electric field. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-interface degradation, was obtained by HPA. Our results show that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited reliability penalty compared to best-in-class Si-passivated SiGe devices.

Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

Monolayer-Si-passivated Ge nFETs with high electron mobility (175 cm²/Vs at Ns=5×10¹² cm^-2) and superior PBTI reliability (max. V_ov = |V_g-V_th| of 0.28V at 125°C) at 0.95-nm-EOT are demonstrated on a 300 mm Si wafer platform. The electron mobility is increased by optimizing the Si thickness while significant improvement in PBTI reliability is realized by band engineering using La-induced interface dipole and defect passivation using laser annealing. This is a significant step forward for the introduction of Ge nFET as high mobility device in advanced technology nodes.

First demonstration of 15nm-W FIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G_M,SAT,EXT / SS_SAT of 250 μS.μm^-1 / 130 mV.dec^-1 (at the targeted V_DS=0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

Improved Channel Hot-Carrier Reliability in

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high- k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG ~ VD/2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis.

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Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14-16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.

-FinFETs With Replacement Metal Gate by a Nitrogen Postdeposition Anneal Process

For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.