K.-Y. Toh

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated.<<ETX>>

Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology

The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction engineering, and emitter-base (EB) junction engineering. High f/sub T/ Si (30-50 GHz) and SiGe (50-70 GHz) epi-base devices were integrated with trench isolation and polysilicon load resistors to evaluate ECL (emitter coupled logic) circuit performance. A 15% enhancement in ECL circuit performance was observed for SiGe relative to Si devices with similar base doping profiles in a given device layout. Minimum SiGe-base ECL gate delays of 24.6 ps (8 mW) were obtained. Lightly doped spacers were positioned in both the EB and CB junctions to tailor junction characteristics (leakage, tunneling, and avalanche breakdown), reduce junction capacitances, and thereby obtain an overall performance improvement.<<ETX>>

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power advantages of the circuit have been demonstrated in a double-poly, trench-isolated, self-aligned bipolar process with 0.8- mu m (mask) emitter width. Unloaded gate delays of 21 ps at 4.1 mW/gate, 23 ps at 2.1 mW/gate, and 35 ps at 1.1 mW/gate have been measured. >

A 27 GHz 20 ps PNP technology

Summary form only given. A high-performance double-poly p-n-p technology, with features allowing it to be easily integrated into a more general complementary bipolar process, is described. These advanced p-n-p transistors have 80-nm-wide ion-implanted bases and optimized emitter and collector dopant profiles and are fabricated on a thin p-type epilaver in order to achieve high collector current driving capability. The devices have a measured cutoff frequency of 27 GHz, making them the fastest silicon p-n-p bipolar transistors reported to date. Experimental results on the device characteristics are presented.<<ETX>>

A 23 ps/2.1 mW ECL gate

Simulated output waveforms at 0.1, 0.3 and, 0.6-pF loading of a design optimized for a 0.3-pF nominal load are shown. An AC-coupled APD ECL (active-pull-down emitter-coupled-logic) gate with significantly improved gate delay in the low-power (1-2 mW) regime is described. Unloaded gate delays of 23 and 35 ps at 2.1 and 1.1-mW/gate power, respectively, were demonstrated in a bipolar technology using a double-poly, self-aligned process with emitter width of 0.8 mu m (mask). The device cross-section is presented along with an SEM (scanning electron microscopy) micrograph of the basic gate used in the ring oscillator.<<ETX>>

The design and optimization of high-performance, double-poly self-aligned p-n-p technology

The device design and performance of double-poly self-aligned p-n-p technology, featuring a low-resistivity p/sup +/ subcollector, thin p-epi, and boron-doped poly-emitter are described. Device isolation is provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (>or=40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm and base widths of less than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were obtained, and the AC performance was demonstrated by an NTL-gate delay of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. The matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits. >

Sub-30ps ECL circuits using high-f/sub T/ Si and SiGe epitaxial base SEEW transistors

A high-performance bipolar technology is presented which involves Si and SiGe epitaxial base formation in a selective epitaxy emitter window (SEEW) structure. Si transistors have cut-off frequencies (f/sub T/) of 35-53 GHz while the f/sub T/ of SiGe devices ranges from 45 GHz to 63 GHz. The SEEW structure allowed emitter width reduction to 0.35 mu m using optical lithography with 0.8 mu m minimum linewidth to operate the device at high current density near maximum f/sub T/. The ECL (emitter coupled logic) gate delay is examined as function of the trade-off between f/sub T/ and intrinsic base resistance and of the main device parasitics, i.e., base resistance and collector-base capacitance. A minimum ECL gate delay of 24.3 ps was realized in an unloaded ECL ring oscillator.<<ETX>>

A 26 ps self-aligned epitaxial silicon base bipolar technology

A self-aligned epitaxial base technology is presented which allows fabrication of advanced bipolar devices with 40 to 60 nm basewidths and implementation of novel profile design concepts. The viability of this technology for advanced bipolar circuits has been examined by fabricating ECL ring oscillators, thus demonstrating that fully scaled epi-base devices can be successfully integrated. Devices with current gains of 80-90 and intrinsic base sheet resistances less than 10 k&Omega;/sq were fabricated. Epitaxial technology was used to position a novel lightly doped collector (LDC) spacer within the base collector junction of these heavily doped, thin-base devices to control avalanche breakdown and increase BVCEO. Conventional and active pull-down ECL ring oscillators with minimum gate delays of 40.5 and 26.3 ps, respectively, were fabricated with devices showing a measured cutoff frequency of 19.6 GHz

A 1.9 ns/6.3 W/256 Kb bipolar SRAM design

The authors describe the circuit design techniques used to demonstrate the feasibility of achieving a high-speed bipolar split-emitter MTL SRAM with 256 Kb density using ECL (emitter coupled logic) peripheral circuits. A simulated access time of 1.9 ns is achieved at 6.3 W total chip power dissipation, which is below the packaging limit for the intended applications. The minimum simulated cycle time is 3 ns. These results are based on an 0.8- mu m, 26-GHz f/sub T/, double-polysilicon self-aligned bipolar technology with calibrated NPN device models. To achieve this speed and power performance at 256 Kb density, several innovative circuit techniques are used, including an array architecture, an over-writing ECL logic circuit, an address decoder circuit with active pulldown, and bit-line discharge and restore schemes.<<ETX>>