M. B. Zahid

Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks

Trap spectroscopy by charge injection and sensing (TSCIS) is a new, fast and powerful material analysis technique that provides detailed information on the trap density profile and trap energy level in dielectric materials. We show the measurement principle and explain the data analysis. The technique is applied to a number of example materials: SiO₂, Al₂O₃, and Si₃N₄. We show that TSCIS has excellent resolution and is capable of distinguishing between different process-variations.

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.

An Assessment of the Location of As-Grown Electron Traps in

Replacing SiON by high-kappa layers is a pressing issue for CMOS technologies. The presence of as-grown electron traps in HfO2 is a major obstacle, since they can induce threshold-voltage instability, reduce electron mobility, and result in early breakdown. Their location has not been clarified and is addressed in this letter. By selecting test conditions carefully and using samples with a progressive reduction of HfO2 thickness, the authors are able to rule out that traps are piled up near the HfO2/HfSiO interface. A uniform distribution throughout HfO2 does not agree with the test data, either. Results support that trapping is negligible near to one or both ends of the HfO2 layer when compared with trapping in the central region

hboxHfO_2

This paper reports on a comprehensive on-state reliability evaluation on depletion-mode (VTH~-4V) AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) with a bi-layer dielectric (in-situ Si3N4/Al2O3). We have studied the strength and the lifetime of the dielectric to breakdown by means of a Time Dependent Dielectric Breakdown (TDDB) experiment performed at 200°C and the trapping effects induced by applying a positive gate voltage stress. Additionally, for the first time, we have studied the effect of the on-state stress as a function of the drain voltage. The results show that 1) Based on a Time Dependent Dielectric Breakdown (TDDB) evaluation, an applied gate voltage stress of +6V for the lifetime of 20 years can be extrapolated at 200°C. 2) By fitting with a power law, applying +1V gate voltage for 20 years leads to a threshold voltage shift of 0.2V. This guarantees a good reliability margin when these devices are used in cascode switching circuit applications. 3) A new mechanism of high junction temperature thermal de-trapping was observed during a high drain bias stress.

/HfSiO Stacks

We applied the developed trap spectroscopy by charge injection and sensing to validate the extraction of the silicon nitride trap distribution (both in space and energy) from the modeling of retention transients of charge-trapping memories. We compared three different types of silicon nitrides using these two techniques, and similar distributions were extracted, thus confirming the validity of the charge profiles resulting from the modeling of retention transients and the physics of the proposed model, based on two main mechanisms of charge loss: Poole-Frenkel emission (dominating at high temperature) and direct tunneling (dominating at room temperature).

Comprehensive investigation of on-state stress on D-mode AlGaN/GaN MIS-HEMTs

TANOS charge trap flash (CTF) with Al₂O₃-Si₃N₄-SiO₂ memory stack and TaN metal gate is a candidate technology to replace conventional floating gate technology for multi-level NAND applications beyond the 32nm node. The main drawbacks of TANOS to date are poor erase performance (in terms of speed and/or saturated level) as well as insufficient retention in the highest programmed state.

Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories

The operation and reliability of nonvolatile memory concepts based on charge storage in nitride layers, such as TANOS (TaN/Al₂O₃/Si₃N₄/ SiO₂/Si), require detailed information on the energy and spatial distribution of the charge defects in both the nitride and the Al₂O₃ blocking dielectric. This paper focuses on the characterization of Al₂O₃. We have successfully applied complementary trap characterization techniques to crystalline γ-phase- Al₂O₃ in order to obtain a complete picture of the spatial and energetic distribution of the defect density. As a result, two defect types at energy levels 1.8 and 3.5 eV below the conduction band edge are found.

Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory

We find that off-state breakdown in AlGaN/GaN insulated-gate HEMTs can occur at the source-side of the gate with increase in the drain voltage. This new finding is borne out by extensive electrical measurements and confirmed with the OBIRCH (Optical Beam Induced Resistance CHange) technique. It is explained by a hypothesis whereby holes generated at high Vds flow to the source-side of the gate, and due to the low valence band offset, enter the gate insulator and damage it. Holes also cause threshold voltage shifts that turn the device on. The damage occurs in discrete spots, as would be expected by defects. Finally, we show improved breakdown voltage with a better gate-dielectric interface.

Applying Complementary Trap Characterization Technique to Crystalline

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH-evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly di electrics. In this paper, we show results on Al2O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials.

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The goal of this letter is to investigate and characterize the defects at the Al2O3/gate interface in TANOS memory stacks. To this purpose, gate-side trap spectroscopy by charge injection and sensing is applied on devices featuring different metal gates and different postdeposition anneals. The results show that a high concentration of defect is present in crystalline samples with a TaN or TiN gate.