Gilles Masson

A 1 nJ/b 3.2-to-4.7 GHz UWB 50 Mpulses/s double quadrature receiver for communication and localization

This paper describes the integration in a 0.13 µm CMOS of an Ultra Wide Band (UWB) receiver for communication and localization. It operates in the whole 3.2-to-4.7 GHz band of the IEEE.802.15.4a regulation mask. The proposed double quadrature coherent architecture allows exploiting high resolution capability of short pulses in the time domain, with a low sampling clock at 50 MHz. Architecture offers high flexibility to cope with various channel conditions and robustness against out of band blockers. Maximum measured ranging error at 4m in wireless link is 3.8 cm and total receiver consumption at 50 Mpulses/s rate is 50 mW.

Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision

The interest of industry for localization technologies is growing, because of their ability to allow a wide variety of applications. Among the different technologies, UWB is known to potentially offer the best precision. This paper presents a fully integrated low-power UWB impulse radio receiver dedicated to communication and ranging applications. The new architecture based on double quadrature is used to reach sub-cm ranging precision while limiting the speed requirements and complexity of ADC and digital signal processing. Much attention has been paid to rejecting the out-of-band signals which could degrade receiver performance while fully exploiting the available spectrum in the [3-5 GHz] band. The 5.8-mm2 0.13- μm CMOS receiver consumes 50 mW at 50-Mb/s maximum data rate. It shows -95-dBm sensitivity at 1 Mb/s and 2.5-mm maximum ranging error at 10 m.

UWB beamforming architecture for RTLS applications using digital phase-shifters

In this paper a novel solution for coherent combination in ultra wide band (UWB) beamformings for real time locating systems (RTLS) is proposed. The architecture uses a double quadrature receiver and the time alignment is approached by digital phase-shifters. A comparison and evaluation with classical True Time delay (TTD) architectures is presented. Our proposed architecture achieves same performances than the TTD approach, showing that complex TTD modules could be replaced advantageously by a single base-band digital phase shifters. Moreover, our solution does not need higher sampling rates that make it suitable for low power consumption.

A 4GHz CMOS 130 nm IR-UWB dual front-end transceiver for IEEE802.15 standards

A single chip CMOS 130 nm transceiver for UWB-IR communications was assembled and measured for further integration into a demonstrator aiming compatibility with the recently published IEEE802.15.6 standard for Body Area Networks. The transmitter achieves a 10.9 mA current consumption for the 15.6MHz pulse repetition frequency and 1.5V peak-to-peak voltage. The receiver is an innovative combination of a low current consumption non coherent envelop detector and of a high sensitivity coherent quadrature demodulator. Different compromises in sensitivity, current consumption and acquisition speed are made possible. This paper briefly describes the architecture and provides the chip measurement results.

Digital Radio Front-End for High Data Rate Impulse UWB System

This paper presents on overview of the two chip integration of a digital radio receiver for wireless communication systems based on ultra wideband (UWB) impulse radio technology. The chips have been integrated in a 130 nm CMOS technology. The front-end performs 1-bit direct sampling of the RF signal. The baseband processing is implemented in a FPGA. The UWB link demonstration runs at 78.125Mpulse/s using polarity and a coding rate of 1/2 which gives a maximum information data rate of 39.1Mb/s (limited by the highest FPGA demodulation rate).

Antenna characteristics and ranging robustness with double quadrature receiver and UWB impulse radio

This paper analyzes the effect of the antenna characteristics on the ranging precision of UWB impulse radio receivers. It shows that the influence of the antenna highly depends on the chosen RF architecture. The single quadrature receiver architecture is first explained and analyzed. Then the double quadrature receiver is presented and its robustness is justified. A small size miniaturized ultra wideband antenna is then described. This antenna is exploited to validate the robustness thanks to link level simulations.

A CMOS Duty-Cycled Coherent RF Front-End IC for IR-UWB Systems

Current consumption of an IR-UWB receiver is reduced thanks to duty-cycling techniques applied to the full analog chain, thus benefiting from the impulsive nature of the signal. The coherent architecture performs down conversion by mixing the incoming pulse with a locally generated 2.75ns pulse template and needs only a 1GHz frequency synthesis instead of a power hungry 4 or 8 GHz LO. Duty cycling with sub-ns settling time enables up to 82% current savings for the front-end at a 15.6MHz pulse repetition frequency. To operate in a strong interference environment, an optional 4th order Gm-C filter may be switched on. The receiver for IR-UWB communications and ranging is implemented in CMOS 130nm and measurement results confirm the expectations.

UWB: innovative architectures enable disruptive low power wireless applications

This work presents the potential offered by new UWB pulse radio transceiver designs. It shows that a judicious architecture selection can be used to exploit the benefit of impulse radio and to reach state of the art performances both in energy efficiency and ranging accuracy The first presented architecture is dedicated to localization application whereas the second one is focusing on high speed and remote powered radio link for the application of ambient intelligent. After a brief description of the application area, the selected architecture are described and justified. Then, the chipset design is presented and the measurements results are summarized. Lastly, perspectives are drawn from the combination of those two developments.