Giuseppe La Rosa

A review of hot-carrier degradation mechanisms in MOSFETs

We review the hot-carrier effects and reliability problem in MOSFET. The mechanisms that produce the substrate and gate current are discussed, and the various mechanisms for hot-carrier degradation are presented. DC and AC lifetime models are summarized, and the effects on a CMOS circuit explained. The effects of scaling on the hot-carrier induced degradation are presented and the influence of processing steps and stress temperature discussed. Ways to improve the reliability of MOSFETs are then presented. Finally the reliability of SOI MOSFETs is compared to that of bulk MOSFETs.

Trade-Offs Between RF Performance and Total-Dose Tolerance in 45-nm RF-CMOS

The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping.

Impact of Source/Drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs

We report the radio frequency (RF) stress reliability response of 45-nm SOI RF nMOSFETs. The dependence of gate oxide degradation and off-state leakage (due to RF stress) on the contact spacing of the Source/Drain (S/D) terminals and the gate finger-to-gate finger spacing is investigated. The RF device performance trade-offs vs. RF stress reliability that result are investigated. Devices with “tight” S/D contact spacing have improved RF performance but worse RF reliability than devices with “loose” S/D contact spacing. Devices with “loose” gate-finger to gate-finger spacing have better RF performance and also better RF reliability. The net result of this investigation is that fundamental tradeoffs between RF performance and reliability exist at these advanced scaling nodes.

Mechanical stress effects on p-channel MOSFET performance and NBTI reliability

Because of the strong sensitivity to gate oxide processing it has been difficult to compare and correctly quantify the effect of pure mechanical stress on the MOSFETs with different level of device stress engineering. We report, for the first time, a detailed evaluation of the impact of mechanical compressive and tensile stress on device performance and NBTI reliability of p-MOSFET devices with identical gate oxide. These effects were investigated by exploiting the well known induced mechanical effects on devices placed in proximity to Through Silicon Vias (TSV) [1,2]. A detailed electrical device characterization at time-zero (pre-NBTI stress) confirms a p-MOSFET mobility modulation dependence on proximity to TSV, device channel orientation and device temperature, consistent with the underlying Cu directional tensile and compressive mechanical stress dependence on Si. It is found that the NBTI induced Threshold Voltage shift is not affected by the mechanical stress. On the contrary, it is found that the NBTI component contributing to mobility degradation is strongly dependent on the level of the applied mechanical stress. This finding gives some further insights on the nature of the NBTI damage.

Improving reliability through nitrogen purge of carriers

Decreasing insulator thickness at many levels of recent technology nodes raises concern for reliability. We apply a stress test inline, using a specially designed structure. It was found that reliability was strongly affected by queue time between a dry and wet etch step of a spacer, likely due to remaining RIE induced damage. By applying nitrogen purge of the wafer carrier the susceptibility to failure can be completely eliminated. This points to a fail mechanism related to residual etch products.