Stewart E. Rauch

Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations

It is now well established that the negative bias temperature instability (NBTI) mechanism alters both the mean and variance of the distribution of the PFET under stress. This effect has reliability implications to balanced analog circuits (e.g., current mirrors, differential pairs, etc.), as well as to SRAM cell stability. This paper presents a brief review of the understanding and models to date of the statistics and impacts of the NBTI-induced variation. This is followed by a critical examination of the actual NBTI-induced distributions and the accuracy of the normal approximations that have been used to date.

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies

In this work the reliability of a 0.35 /spl mu/m p+ poly-gate pMOSFET CMOS technology under conductive channel hot carrier conditions is investigated. It is found that at any bias and temperature condition applied, the degradation of sufficiently short channel length (Leff/spl sime/0.14 um) devices results in a reduction in drive current due to the impact of donor type interface trap generation and positive charge formation during the stress. At these dimensions the degradation is controlled by a contribution of both Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) mechanism. We will show the role that each of these two mechanisms play in determining the shift of typical device parameters. A methodology to decouple the two effects is also provided allowing to quantify each contribution separately at any bias and temperature condition. A conductive CHC model that takes into account the impact of both mechanisms to the device lifetime at the worst observed degradation condition (Vg=Vd) is also discussed.

The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.

Role of E-E scattering in the enhancement of channel hot carrier degradation of deep-submicron NMOSFETs at high V/sub GS/ conditions

It has been reported in the literature that in deep-submicron nMOSFETs, the worst channel hot carrier (CHC) degradation is not near the peak substrate current (as predicted by the lucky electron model), but at the V/sub GS/=V/sub DS/ bias condition. We propose a new CHC model based on an electron-electron scattering-induced hot carrier (HC) mechanism, that explains the worsening of the HC damage at high VGs and agrees well with the HC lifetime measured over the moderate to high gate voltage range and a wide L/sub EFF/ range. The predicted quadratic source current dependence of HC lifetime at mid V/sub GS//V/sub DS/, evolving into a cubic dependence at high V/sub GS//V/sub DS/, matches well the observed behavior.

The energy driven paradigm of NMOSFET hot carrier effects

As NMOSFET size and voltage are scaled down, the electron energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high field region. A new paradigm of NMOSFET hot carrier behavior is proposed here, in which the fundamental driving force is available energy, rather than peak lateral electric field as it is in the lucky electron model (LEM.) This approach allows an experimental determination of S/sub IT/ (the interface state generation cross section) as a function of electron energy.

High-

Recently, negative bias temperature instability (NBTI) enhanced by local self-heating has been proposed as a mechanism for high-Vg PFET ¿hot-carrier¿ degradation. This is based on the idea that the effective temperature for NBTI is increased in the drain region due to a very localized self-heating effect reported in the literature by Pop and others. Our PFET dc stress data are consistent with local self-heating activated NBTI at high Vg , but at mid Vg, we observed similar behavior to typical NFET hot carriers, i.e., energy-driven hot carrier (EDHC). If self-heating is involved with the PFET high-Vg dc degradation, the question of ac behavior naturally arises. Our PFET ring-oscillator stress results demonstrate that the high-VGS PFET hot carrier dominant under dc stress does not significantly contribute under typical CMOS switching conditions, whereas the mid-VGS hot carrier does. This supports the idea that the predominant damage mechanism involved at high VGS is NBTI enhanced by local self-heating with a thermal time constant longer than a few hundred picoseconds.

V_{\rm GS}

New alpha counters make accurate measurements of low emissivity samples possible. Modeling results set lower limits for measurements at sea level of silicon substrates to about 0.3 α/khr-cm2. Our measurements demonstrate the effect of cosmic ray shielding on the measured alpha-particle emissivity. A few atoms of radon contamination can cause elevated emissivities many days after exposure.

PFET DC Hot-Carrier Mechanism and Its Relation to AC Degradation

It has been reported in the literature (Rauch et al., 1998; Wang-Ratkovic et al., 1997; Su et al, 1996; Li et al., 1999) that in deep submicron NMOSFETs the worst channel hot carrier (CHC) degradation is not near the peak substrate current (as predicted by the lucky electron model (Hu et al., 1985)), but at the V/sub GS/=V/sub DS/ bias condition. We propose a new CHC model based on an electron-electron scattering induced hot carrier mechanism, that explains the worsening of the HC damage at high V/sub GS/ and agrees well with the HC lifetime measured over the moderate-to-high gate voltage range and a wide L/sub EFF/ range. The predicted quadratic source current dependence of HC lifetime at mid V/sub GS//V/sub DS/, evolving into a cubic dependence at high V/sub GS//V/sub DS/, matches the observed behavior well.

Ultra-Low Emissivity Alpha-Particle Detection

Stress-induced void growth is modeled for the case of a void bounded by two neighbors by invoking the one-dimensional diffusion equation. The resultant equation is then convoluted with an exponential distribution for void spacing to generate the mean void size as a function of time. Volumetric strain, atomic diffusivity and activation energy are then extracted for a given metallization and passivation system by fitting measured mean void size data to the analytical curve.