Grace Huiqi Wang

Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications

The device physics and electrical characteristics of the germanium (Ge) tunneling field-effect transistor (TFET) are investigated for high performance and low power logic applications using two dimensional device simulation. Due to the high band-to-band tunneling rate of Ge as compared to Si, the Ge TFET suffers from excessive off-state leakage current Ioff despite its higher on-state current Ion. It is shown for the first time that the high off-state leakage due to the drain-side tunneling in the Ge TFET can be effectively suppressed by controlling the drain doping concentration. A lower drain doping concentration reduces the electric field and increases the tunneling barrier width in the drain side, giving a significantly reduced off-state leakage. To increase Ion with a steeper subthreshold swing S, source doping concentration is increased to reduce the bandgap and narrow the tunneling width. Device design and physics detailing the impact of drain and source engineering on the performance of Ge TFET ar...

Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization

The device physics of the double-gate tunneling field-effect transistor (DG TFET) is explored through two dimensional device simulations. The on-state drain current Ion of the DG TFET, which is based on band-to-band tunneling, has a strong dependence on the silicon film thickness TSi and the physics governing it is detailed. It is established that band-to-band tunneling at the surface is very strong and accounts for a large part of the total drain current. However, a substantial part of the total drain current Ids is contributed by a subsurface portion of the silicon film. Detailed potential distributions show that the coupling of two gate electrodes in the DG TFET could effectively reduce the tunneling width ωT at the center of the silicon film up to an optimum TSi where maximum drain current is obtained.

Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction

The device physics and guiding principles for the design of the double-gate tunneling field-effect transistor with silicon-germanium (SiGe) heterojunction source are discussed. Two dimensional device simulations were employed to study the influence of the position of the SiGe∕Si heterojunction on band-to-band tunneling and device performance. It is established that band-to-band tunneling occurs at a distance of ∼4nm from the gate edge in the source region. In order for the narrower bandgap of SiGe to play a dominant role, the overlap between the SiGe region and the gate should be such that the whole tunneling path of the electrons is located in SiGe. To harness the maximum benefits of the high band-to-band tunneling rate in SiGe, an overlap of ∼2nm between the SiGe region and the gate would be required.

Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source

A novel double-gate (DG) tunneling field-effect transistor (TFET) with silicon–germanium (SiGe) Source is proposed to overcome the scaling limits of complementary metal–oxide–semiconductor (CMOS) technology and further extends Moores law. The narrower bandgap of the SiGe source helps to reduce the tunneling width and improves the subthreshold swing and on-state current. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. For the first time, we show that such a technology proves to be viable to replace CMOS for high performance, low standby power, and low power technologies through the end of the roadmap with extensive simulations.

Strain and Materials Engineering for the I-MOS Transistor With an Elevated Impact-Ionization Region

An impact-ionization MOS (I-MOS) transistor with an elevated impact-ionization region (I-region) or the L-shaped I-MOS (LI-MOS) transistor has been proposed as a promising candidate among various I-MOS structures for enhanced performance through strain and materials engineering. The elevated I-region allows for the incorporation of novel materials to induce strain and reduction in the bandgap to increase the impact- ionization activity. In addition, the LI-MOS structure is more compact and compatible with conventional CMOS processes. In this paper, we discuss and explore the relationship and impact of strain and bandgap on the generation of impact-ionization carriers. Si n-channel I-MOS transistors with Si raised source/drain (RSD), Si1-yCy RSD, and Si1-xGex RSD were studied and explored through simulations and experiments. An excellent subthreshold swing of sub-5 mV/dec at room temperature is demonstrated for the three I-MOS transistor structures. Compared to an unstrained I-MOS with Si RSD, strain-engineered I-MOS with Si0.99C0.01 RSD exhibits a twofold enhancement in both ON-state current and maximum transconductance at a gate length of 60 nm. For materials- or bandgap-engineered I-MOS with Sio.75Ge0.25 RSD, a greater enhancement of approximately three times is observed. In addition, a lower breakdown voltage and enhanced breakdown characteristics are achieved with both strain- and materials-engineered I-MOS transistors.

I-MOS Transistor With an Elevated Silicon–Germanium Impact-Ionization Region for Bandgap Engineering

An impact-ionization MOS (I-MOS) transistor with an elevated impact-ionization region (I-region) and excellent subthreshold swing of 3.2 mV/dec at room temperature is demonstrated. An elevated Si_0.75Ge_0.25 region is integrated and employed to engineer the bandgap and impact-ionization rate in the I-region. Compared to a device with a Si I-region, an I-MOS device with a Si_0.75Ge _0.25 I-region shows significantly enhanced performance due to the smaller bandgap of the I-region and the enhanced impact-ionization rate. For the I-MOS device with a Si_0.75Ge_0.25 I-region, the breakdown voltage is also reduced, and a significant drive current enhancement is achieved at V_G-V_T=1 V and a gate length of 80 nm

A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor

This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor technology that achieves subthreshold swing well below 60 mV/decade at room temperature. First, the LI-MOS transistor is CMOS process compatible, and requires little process modification for integration in a manufacturable process. Second, the LI-MOS structure employs raised source/drain (S/D) regions that enable controllability and scalability of the impact ionization region (I-region). Third, the LI-MOS has superior compactness over previously reported I-MOS device structures. Fourth, the LI-MOS enables the integration of novel materials for band gap and strain engineering to enhance the impact ionization rate in the I-region. Based on the above technology, we demonstrate a record subthreshold swing of 4.5 mV/decade at room temperature for a 100 run gate length device that incorporates a SiGe I-region. The smallest impact-ionization-based MOS device with a gate length of 60 nm is also demonstrated with a subthreshold swing that is well below 60 mV/decade

Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering

The introduction of lattice strain in impact-ionization metal-oxide-semiconductor (I-MOS) transistors for performance enhancement is reported. Lattice strain affects impact ionization and its impact on device performance is explained in relation to the physics of I-MOS device operation. By integrating epitaxial silicon-carbon (Si0.99C0.01) source and drain regions in a complementary-MOS-compatible fabrication process, strained n-channel I-MOS devices were fabricated. Tensile strain in the channel and impact-ionization regions contributes to enhanced electron transport and device characteristics. The strained I-MOS technology demonstrates an excellent subthreshold swing of 5.3mV∕decade at room temperature. Compared to control I-MOS devices with Si raised source/drain, strained I-MOS devices show significantly higher drive current and a steeper subthreshold swing.

Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealing

Incorporation of tin (Sn) in substitutional sites in strained Si0.75Ge0.25 was demonstrated by Sn implant and pulsed laser annealing. The surface of Si0.75Ge0.25 was amorphized by Sn implant but was recrystallized after pulsed laser annealing. The crystalline Si1−x−yGexSny layer formed was studied by Rutherford backscattering spectrometry and Raman spectroscopy. A substitutionality up to 62% Sn and 80% Ge was obtained at an optimal laser power of 400mJcm−2 for five laser pulses. A compressive strain of −1.15% was also obtained due to Sn incorporation. The presence of Sn also increased the active B dopant concentration in activating Si1−x−yGexSny to give low sheet resistance. The implantation of Sn and B followed by pulsed laser annealing could be useful for application in strain engineering of high mobility metal-oxide-semiconductor field-effect transistors.

High quality silicon-germanium-on-insulator wafers fabricated using cyclical thermal oxidation and annealing

An improved fabrication scheme for forming strained SiGe on insulator (SGOI) is demonstrated. Cyclical thermal oxidation and annealing (CTOA) process is introduced to mitigate issues associated with surface roughening and nonuniformity due to increased germanium (Ge) content during SiGe oxidation. Annealing in an inert ambient can be introduced between each oxidation phase to homogenize the Ge content. The root-mean-square surface roughness of the SGOI layer is evaluated to be 0.41nm. With CTOA, a high quality SGOI substrate is obtained. This technique is promising for the fabrication of dislocation-free SGOI layers for applications in high mobility metal-oxide-semiconductor field-effect transistors.