Grzegorz Łabiak

Symbolic State Exploration of UML Statecharts for Hardware Description

The finite state machine (FSM) and Petri net theories have elaborated many techniques and algorithms that enable the employment of formal methods in the fields of synthesis, testing, and verification. Many of them are based on symbolic state exploration. This paper focuses on the algorithm of the symbolic state space exploration of controllers specified by means of statecharts. Statecharts are a new technique for specifying the behaviour of controllers, which, in comparison with FSM and Petri nets, is enriched with notions of hierarchy, history, and exception transitions. The paper presents the statechart diagrams as a means of digital circuit specification.

Statechart-based design controllers for FPGA partial reconfiguration

Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in authors proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.

Concurrent processes synchronisation in statecharts for FPGA implementation

In this paper useful methods of concurrent processes synchronization in UML state machine diagrams are presented. It is not easy to transform complex behaviour description into statecharts, even if the formal specification has already been given, for example as a hierarchical Petri net. Both graphical forms of specifications can be used simultaneously, especially when overlapped concurrent processes are considered. The authors specify the behaviour of an industrial chemical controller as a case study to demonstrate the way of transforming the verbal specification through a formal Petri net model into the UML format, which is more and more frequently understood and widely accepted by industry. The diversification of description gives a chance that the obtained design result, which can be seen both from theoretical and practical points of view, will be correct. The specification is considered from a reconfigurable hardware implementation side and a digital design methodology. It is based on hierarchical concurrent state machine implementation through state encoding into mapping into FPGA matrices, supported by hardware description languages, for example VHDL. In the paper some effective process synchronization methods are included: by introducing global variables and using UML graphical synch states accepted by the UML standard. The proposed methodology is fully supported by system HiCoS, developed at the University of Zielona Góra for a rapid prototyping of reconfigurable logic controllers.

Logic synthesis of n-ary quantitative relations

This contribution shows how to express mathematical abstract notion of n-ary relation by means of Boolean equations. The main criterion of the relation examined in the paper is quantitative criterion, where elements of the domain sets of the relation can be compared just like ordinal numbers, that is can be greater than, equal to or greater or equal to.

A method of transition conflict resolving in hierarchical control

The paper concerns the problem of automatic solving of transition conflicts in hierarchical concurrent state machines (also known as UML state machine). Preparing by the designer a formal specification of a behaviour free from conflicts can be very complex. In this paper, it is proposed a method for solving conflicts through transition predicates modification. Partially specified predicates in the nondeterministic diagram are transformed into a symbolic Boolean space, whose points of the space code all possible valuations of transition predicates. Next, all valuations under partial specifications are logically multiplied by a function which represents all possible orthogonal predicate valuations. The result of this operation contains all possible collections of predicates, which under given partial specification make that the original diagram is conflict free and deterministic.

UML Support for Statecharts-Based Digital Logic Controller Design in FPGA Technology

The paper describes usage of UML methodology in digital logic control modeling, which is one of few stages of digital logic controller development life cycle. The digital logic control modeling process is compared with traditional and well known software development methodology. In the comparison the differences are particularly emphasized. The main differences are connected to analyzing process and modeling aims. In case of software development crucial role plays object analysis which is meant to bring creation of data model. In case of digital logic controller design main activity in modeling is behavior analysis which is aimed to specify formally and precisely controller behavior.

Detection of Possible Frozen States in Communicating UML State Machines

Abstract One of the most important problems of verification of discrete event control systems is detection of possible incorrect communication between concurrent processes, such as mutual blocking. Processes can be modeled as state machines, and such detection can be performed by analysis of behavior of the communicating automata. For such analysis in general case the model checking methods are used, nevertheless some practically important results can be obtained by the methods with lower computational complexity. In the paper a special case of the problem is considered, which is a detection of possible frozen states in a pair of communicating state machines. The algorithm solving this task is presented, its computational complexity is evaluated.

Statechart Diagrams Implementation in FPGA Structures with Embedded Memory Blocks

Abstract Statechart diagrams, also called state machines, are graphic formalism for behavior description of complex systems. One of many applications of statecharts is description of reactive systems, especially digital controllers. There are many strategies of statecharts-based controller implementations, but there is no universal one. In the paper authors have presented new synthesis algorithms. Statecharts diagrams, through FSM form, are transformed into memory blocks using address register and ROM memory with reduced memory size obtained by the introduction of address modification. Good feature of the new algorithm is usage of dedicated Embedded Memory Blocks, whereas traditional logic cells can be used for other purposes.

B05: Transition conflicts detection in binary modular statecharts diagrams 1

Abstract Statechart diagrams are graphic formalism for modelling digital controller behaviour. Statecharts employ notion of traditional state transition graph enhanced with concurrency, hierarchy and broadcast communication. One of undesirable problem which arises in specifying behaviour in this way is undeterministic situation, where at given instant of time, two or more transitions can move activity from one state. If this happens, the transitions are said to be in conflict. Conflicts can be both horizontal and, because of hierarchy, vertical. In the paper two methods of searching for conflicting transitions are presented: static based on hierarchy diagram and dynamic using characteristic function of space of global states.