Gustaf Winroth

Quantification of shot noise contributions to contact hole local CD nonuniformity

As feature sizes continue to shrink, the discrete nature of light and matter is becoming a significant contributor for the variations observed in lithography in general and for EUVL in particular. Owing to the 15x higher energy of EUV compared to ArF photons and similar, if not lower, exposure doses, the number of photons per unit area in EUV is significantly reduced. If the number of photons per contact hole is considered, the situation is even more dramatic, as the target area of a contact is smaller for EUVL than for ArF patterning. The latter argument, however, is less of a concern in the case where the contact hole is fabricated by a negative tone rather than a positive tone process. Since photon shot noise scales with 1/√(#photons), shot noise statistics would favor a brightfield negative tone over a darkfield positive tone process. Indeed, stochastic simulations predict an increase in the number of photons used to delineate a 22nm contact hole structure when printed in EUV using a negative tone instead of a positive tone process. In this paper, we will quantitatively investigate the stochastic nature of the discreet steps in the lithography process and compare the local CDU performance of contact holes for both negative and positive tone processes.

Double patterning with dual hard mask for 28-nm node devices and below

Abstract. A double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80 nm and a lateral critical dimension <30  nm is reported. A full stack for a double patterning approach for etch transfer down to an Si layer, including a hard mask (HM) in which the line and cut patterning are performed, is presented. The importance of the HM in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting a straight profile. All the results shown in this paper have been obtained on 300-mm wafers.

Understanding EUV resist dissolution characteristics and its impact to RLS limitations

In this work we present insights into RLS trade-offs by combining experimental data mining and resist modeling and simulation techniques with a development rate monitor (DRM). A DRM provides experimentally-determined dissolution characteristics for a given resist process and potentially can be used to produce a more accurate model description of the process. This work presents experimentally-determined dissolution characteristics for ultra-thin (50nm) EUV resist films as a function of material type and developer conditions and their impact to RLS trade-offs. Resist models are created with DRM data for its dissolution characteristics and used in subsequent simulations to gain fundamental understanding of EUV lithographic performance. In addition to typical lithographic quality metrics (exposure latitude, DOF), the interaction of resist properties (ie, de-protection kinetics and dissolution) with processing techniques are also discussed. Finally, a description of the RLS trade-off with respect to resist properties and process conditions is discussed.

Roughness and variability in EUV lithography: Who is to blame? (Part 1)

Process variability in today’s EUV lithography might be a showstopper for features below 27nm dimensions. At these feature sizes, electrical devices are influenced by quantum effects and thus have to face the discrete behavior of light and matter. More in general, lithography uncertainties arise from each lithographic element: the source, the photomask, the optical system, and the photoresist. In order to individually assess all the different contributions to the final resist roughness, a EUV mask with known absorber pattern variability was used to expose different resists at different process conditions. CD-SEM analyses were performed on both mask absorber and resist pattern and then used to build a stochastic resist model. In this first paper, we present a complete characterization of the root causes which are responsible of the CD nonuniformity for 27nm half-pitch dense contact-holes exposed with the ASML NXE:3100 scanner installed at imec. Using the same stochastic model, a simulated evaluation to quantify the possible impact of the different elements composing the lithographic process is performed at higher numerical aperture.

193nm immersion lithography for high-performance silicon photonic circuits

Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm- STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of <1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as ~0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to ~0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1×105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm- or standard 193nmbased patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.

Double patterning with dual hard mask for 28nm node devices and below

In this paper, we report a double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80nm and a lateral critical dimension (CD) below 30nm. We present a full stack for a double patterning approach for etch transfer down to a Si layer, including a hard mask in which the line and cut patterning are performed. The importance of the hard mask (HM) in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting straight profile. All the results shown in this paper have been obtained on 300mm wafers.

Relationship between film thickness loss and polymer deprotection for extreme ultraviolet and ArF photoresists

The authors report on the relationship between the film thickness loss (FTL) and the polymer deprotection of chemically amplified resists with chemistries for ArF and extreme ultraviolet lithography. FTL curves are quickly and easily accessed experimentally through in-line ellipsometry measurements. They also provide affordable and valuable input for the description of acid generation and polymer deprotection kinetics for resist modeling. Unlike 248 nm resist platforms, where a linear relationship has been observed between the polymer deprotection and the FTL, they observe that for 193 and 13.5 nm technologies, the polymer composition induces a deviation from this linearity. In particular, the authors use Fourier transform infrared spectroscopy for the evaluation of the polymer deprotection in both model resists (with known chemical properties) and state-of-the-art commercial resists. With the corresponding FTL, chemical components that contribute to the nonlinearity are identified.

Critical material properties for pattern collapse mitigation

Abstract. Modern high-resolution lithography, which employs a chemically amplified resist (CAR) at either 193 or 13.5 nm wavelength, is often limited by pattern collapse. While the general concepts of how CAR platforms work are widely understood, the influence of composition on pattern collapse has been studied to a lesser extent. In addition, the subject is often further complicated by non-disclosure of the resist chemistry used in the lithographic evaluation. Open-source photoresist platforms can be beneficial for fundamental studies on how individual components influence pattern collapse. Such platforms should mimic a typical CAR, containing—apart from the polymer—additional components such as photo acid generators (PAGs) and base quenchers. Here, 193 nm and extreme ultraviolet lithography open-source platforms are presented wherein the chemistry, composition, and concentration are all disclosed. With the aim of fundamentally understand how resist composition and behavior influences pattern collapse, the molecular weight of the polymer backbone and the concentration of both PAG and base quencher were varied. These sets of resists were exposed using high-end optical lithography scanners. The results are presented such that the probability of pattern collapse is derived as a function of the exposure wavelength, chemistry, and component concentrations.

Modeling the lithography of ion implantation resists on topography

With emerging technologies, such as fin-based field-effect transistors (finFETs), the structures, which define the functionality of a device, have added one dimension in the patterning and are now three-dimensional. Lithography for CMOS patterning becomes more complicated for finFETs given the three-dimensional substrate structure, and the resist modeling targeting this issue is yet to be fully investigated. Here, we present lithographic simulations on topography relevant for finFET devices compatible with nodes down to 10 nm. We investigate the influence of different materials and of the additional optical complexity due to the topography and density of the gates and fins.

Precuring implant photoresists for shrink and patterning control

Polymeric photoresists are readily being used as the stopping layer for ions during implantation processes in manufacturing of integrated circuitry. In order to be compatible for standard optical lithography with deep ultraviolet exposures, the state-of-the-art resists are chemically amplified; as they are for photoresists for etch patterning. Partially deprotected, including patterned, photoresists contain a range of small molecular weight species that are prone to escape the resist if the resist was to be irradiated by additional UV-light, electron beams or ion bombardment. For implant processes in device integration this is becoming progressively the most topical issue for aggressive nodes, where 193 nm compatible resists are progressively turning out to be the new platform for implant lithography. These will shrink significantly during the ion implantation and subsequently produce undesired doping gradients on a length scale comparable to the target feature width. In addition, conventional UV-flood exposure that is common for 248 nm resist platforms is not directly transferrable to 193 nm resists. In this paper, we explore the precuring options available for state-of-the-art implant photoresists for 193 nm lithography, in which we target to reduce the shrinkage during implantation for trench critical dimensions that are relevant for nodes below 20 nm. We present an extensive study comprising of different approaches, including laser-, ion- and electronbased treatments. Each treatment is individually investigated with the aim not only to find a valid pretreatment for shrinkage control during implantation, but also to fundamentally understand what effect alternative pretreatments have on the profile and dimensions of thick photoresists used as implant stopping layers. We find that there are viable options for further process optimization in order to integrate them into device process flows. To this extent, we show the shrink behavior after pretreatment and compare the additional shrink dynamics after implantation.